Enumerated Type in assertion ?

M

Marek Ponca

Hello everybody,

last time I have done some simulations with self-test features,
there was a problem of reporting a value of one signal.
It was an array of ennumerated types:


Something like this:
---------
type enum_t is (S1, S2, S3, S4, S5, S6, S7);
type enum_a is array (1 to 5) of enum_t;

constant enum_c : enum_a := (S1, S2, S3, S4, S5);

signal enum_s : natural range of 1 to 5;
....
enum_s <= 3;

assert(FALSE)
report "Value is:"&to_string(enum_c(enum_s))
severity note;
---------

Function to_string was from std_developers_kit.


But this does not work (Modelsim). The enummerated vatues have to be
somehow
converted to string...


Does anybody have a better approach ?

Thanks,
Marek Ponca
 
J

Jonathan Bromley

Something like this:
---------
type enum_t is (S1, S2, S3, S4, S5, S6, S7);
type enum_a is array (1 to 5) of enum_t;

constant enum_c : enum_a := (S1, S2, S3, S4, S5);

signal enum_s : natural range of 1 to 5;
...
enum_s <= 3;

assert(FALSE)
report "Value is:"&to_string(enum_c(enum_s))
severity note;

report "Value is: " & enum_t'image(enum_c(enum(s)))
severity note;

In VHDL-93 there is a built-in "to_string()" function
for *any* scalar type T, called T'image(). There
is a much less useful function T'value() which does
the reverse - it converts a string to its data
value. Unfortunately, there's no way to protect
T'value() against errors. If the input string is
in any way wrong, i.e. it doesn't exactly match
one of the possible results of T'image, then
it bombs the simulation with an error. Consequently,
T'value() is too fragile for any practical use IMHO.
Hey, that's one for VHDL-200x that I hadn't thought of -
T'value() with an error trap.

By the way... are you *sure* you want a signal of
subtype "natural range 1 to 5", rather than a signal
of subtype "enum_t range S1 to S5" ?
--
Jonathan Bromley, Consultant

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