Equations in Vector Range Definitions

[guyanalog]

Is it acceptable to use equations in the vector range description of a signal where the parameters are generics, or does this adversely affect synthesis?


What I have now:

generic(
BYTE_NUM : natural range 10 downto 1 := 3; -- # bytes (used somewhere else)
BYTE_BITS : natural range 10 downto 1 := 24 -- # bits for above bytes
);

signal vec_int : std_logic_vector(BYTE_BITS - 1 downto 0);


What I was thinking of changing it to (eliminates a generic):

generic(
BYTE_NUM : natural range 10 downto 1 := 3 -- # bytes (used somewhere else)
);

signal vec_int : std_logic_vector(8*BYTE_NUM - 1 downto 0);

Does the multiplier generate unwanted logic?

Thanks.

 

[GaborSzakacs]

Is it acceptable to use equations in the vector range description of a signal where the parameters are generics, or does this adversely affect synthesis?


What I have now:

generic(
BYTE_NUM : natural range 10 downto 1 := 3; -- # bytes (used somewhere else)
BYTE_BITS : natural range 10 downto 1 := 24 -- # bits for above bytes
);

signal vec_int : std_logic_vector(BYTE_BITS - 1 downto 0);


What I was thinking of changing it to (eliminates a generic):

generic(
BYTE_NUM : natural range 10 downto 1 := 3 -- # bytes (used somewhere else)
);

signal vec_int : std_logic_vector(8*BYTE_NUM - 1 downto 0);

Does the multiplier generate unwanted logic?

Thanks.

1) Multiplying by a power of 8 doesn't add logic.
2) Any amount of arithmetic that evaluates to a constant at synthesis
time doesn't add logic.
3) I can't imagine what sort of logic could be created to end up with
a variable width std_logic_vector!
4) Wouldn't it be easier and faster to try this on your synthesis tool
rather than posting code to a newsgroup?

 

[Andy]

Gabor's points are very good.

However, multiply/divide (of unsigned quantities) by a constant power of 2 generates a simple shift, usually resulting in zero additional logic.

The concept of constant values is different for simulation and synthesis. In synthesis, it includes such things as for-loop indices. When the for-loopis unrolled, the index value is known for each unrolled iteration. Thus any calculation of index and other constant values is also a constant.

It is possible to describe VHDL functions/procedures which return variable width results, but the width must be constant (see above). As an example, to_unsigned() takes a size argument to determine the size of the result. Onecould define a to_unsigned(natural) function that just returned enough bits to hold the result, based on the value being converted. However, it wouldlikely not be synthesizable unless it was called with a constant (see above) value, which would severely limit its usefulness.

Andy