Error in 8 Shift register right code

[shah_satish2002]

Hello All..

I have problem in my code. I have created code for 8 bit shift register right..

ie my input is 11001011
then in
1st clock :- output should be :- 01100101
2nd clock :- output should be :- 00110010
3rd clock :- output should be :- 00011001
4th clock :- output should be :- 00001100
5th clock :- output should be :- 00000110
6th clock :- output should be :- 00000001
7th clock :- output should be :- 00000000(Ie at the end of clock 8, it should be 0h)

Please correct my code :-

library ieee;
use ieee.std_logic_1164.all;


entity shift is
port(C, SI : in std_logic;
SO : out std_logic);
end shift;
architecture archi of shift is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C)
begin
if (C'event and C='1') then
for i in 0 to 6 loop
tmp(i+1) = tmp(i);
end loop;
tmp(0) = SI;
end if;
end process;
SO = tmp(7);
end archi;

Thanks a lot