error in simulation

[aralimaradsir]

i wrote following code in quartus II and tried to simulate but i am
not getting results what could be the reason can anyone fix it thank
you.

package non is

type matrix is array (0 to 3, 0 to 3)of bit_vector(7 downto 0);

end non;


library ieee;
use ieee.std_logic_1164.all;
use work.non.all;
entity add_key1 is
port(clk:in bit;out matrix);
end add_key1;
architecture abc of add_key1 is
--type matrix is array (0 to 3, 0 to 3)of bit_vector(7 downto 0);
constant m1:matrix:=(("11111111","11111111","11111111","11111111"),
("11111111","11111111","11111111","11111111"),
("11111111","11111111","11111111","11111111"),
("11111111","11111111","11111111","11111111"));
constant m2:matrix:=(("11111111","11111111","11111111","11111111"),
("11111111","11111111","11111111","11111111"),
("11111111","11111111","11111111","11111111"),
("11111111","11111111","11111111","11111111"));
signal m3:matrix;
begin
process
begin
wait until clk='1';
loop1: for i in 0 to 3 loop

loop2:for j in 0 to 3 loop
m3(i,j)<=m1(i,j) xor m2(i,j);

end loop loop2;
end loop loop1;
o<=m3;
end process;

end abc;

 

[Tricky]

i wrote following code in quartus II and tried to simulate but i am
not getting results what could be the reason can anyone fix it thank
you.

package non is

type matrix is array (0 to 3, 0 to 3)of bit_vector(7 downto 0);

end non;

library ieee;
use ieee.std_logic_1164.all;
use work.non.all;
entity add_key1 is
port(clk:in bit;out matrix);
end add_key1;
architecture abc of add_key1 is
--type matrix is array (0 to 3, 0 to 3)of bit_vector(7 downto 0);
constant m1:matrix:=(("11111111","11111111","11111111","11111111"),
("11111111","11111111","11111111","11111111"),
("11111111","11111111","11111111","11111111"),
("11111111","11111111","11111111","11111111"));
constant m2:matrix:=(("11111111","11111111","11111111","11111111"),
("11111111","11111111","11111111","11111111"),
("11111111","11111111","11111111","11111111"),
("11111111","11111111","11111111","11111111"));
signal m3:matrix;
begin
process
begin
wait until clk='1';
loop1: for i in 0 to 3 loop

loop2:for j in 0 to 3 loop
  m3(i,j)<=m1(i,j) xor m2(i,j);

end loop loop2;
end loop loop1;
o<=m3;
end process;

end abc;

It runs fine for me - The output is exactly how I expected, all 0's.
What exactly is the problem?