error in synthesis in vhdl code...

[priyanka24]

Hi...

i have written VHDL code and got simulated correctly.

but getting following error during synthesis::


ERROR:Xst:787 : line 98: Index value <9> is not in Range of array <output_stream>.


what is solution for this plz help me?????

 

[sridars]

Hi, You must have created 8 bit array and assigning the value to 9th bit of same array.
post the code if possible