error when wirting for processor(ERROR:Xst:827)

[suraj.jain]

i am dveloping a pic16c61 mucrocontroller in vhdl...while designing main cpu core....i am not able to include reset conditions...
i am getting fallowing error
ERROR:Xst:827 - D:/vvi_CDAC_PROJECT/synchronouspic/CONTROL_UNIT.vhd line 53: Signal INDF cannot be synthesized, bad synchronous description.
-->
i have included the part of code where reset condition is used and where these registers are loaded with data
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.PIC16C61.all;
-------------------------------------

entity CONTROL_UNIT is
Port ( rst : in std_logic;
--connection to clock divider
Q1 : in std_logic;
Q2 : in std_logic;
Q3 : in std_logic;
Q4 : in std_logic;
Q5 : in std_logic;
--Q6 : in std_logic;
Q7 : in std_logic;
Q8 : in std_logic;
---connection to rom and program counter and stack
stack_ctrl : out std_logic_vector(1 downto 0);
pc_low : out std_logic_vector(7 downto 0);
pc_high : out std_logic_vector(7 downto 0);
inst : in std_logic_vector(13 downto 0);
--EXTERNAL PORTS
PORTA : inout std_logic_vector(4 downto 0);
PORTB : inout std_logic_vector(7 downto 0);
---connection to inst decoder
encoded : out std_logic_vector(13 downto 0);
decoded : in std_logic_vector(5 downto 0);
----connection to ram
rd : out std_logic;
wr : out std_logic;
ram_addr : out std_logic_vector(6 downto 0);
data_out : out std_logic_vector(7 downto 0);
data_in : in std_logic_vector(7 downto 0);
----connection to alu
alua : out std_logic_vector(7 downto 0);
alub : out std_logic_vector(7 downto 0);
aluq : in std_logic_vector(7 downto 0);
alu_opcode : out std_logic_vector(3 downto 0);
bit_no : out std_logic_vector(2 downto 0);
bit_test : in std_logic;
flag_c_in : in std_logic;
flag_c_out : out std_logic;
flag_dc : in std_logic;
flag_z : in std_logic
);
end CONTROL_UNIT;

architecture Behavioral of CONTROL_UNIT is

begin
process(rst,Q1,Q2,Q3,Q4,Q5,Q7,Q8) is
variable inst_reg : std_logic_vector(13 downto 0);
variable op_code : std_logic_vector(5 downto 0);
variable temp_addr: std_logic_vector(6 downto 0);
variable w_reg : std_logic_vector(7 downto 0);
variable temp_data,temp_result: std_logic_vector(7 downto 0);
variable read_ram,temp_c,temp_dc,temp_z : std_logic;
variable inst_nop : std_logic :='0';

-------------------SFR'S
variable INDF : std_logic_vector(7 downto 0);
variable TMR0 : std_logic_vector(7 downto 0);
variable PCL : std_logic_vector(7 downto 0);
variable STATUS : std_logic_vector(7 downto 0);
variable FSR : std_logic_vector(7 downto 0);
variable RPORTA : std_logic_vector(4 downto 0);
variable RPORTB : std_logic_vector(7 downto 0);
variable PCLATH : std_logic_vector(7 downto 0);
variable INTCON : std_logic_vector(7 downto 0);
variable OPTION : std_logic_vector(7 downto 0);
variable TRISA : std_logic_vector(4 downto 0);
variable TRISB : std_logic_vector(7 downto 0);
variable temp_rporta : std_logic_vector(4 downto 0);
variable temp_rportb : std_logic_vector(7 downto 0);
-------------------------------------
begin
if(rst ='1') then
INDF :="00000000";
TMR0 :="--------";
PCL :="11111111";
STATUS :="00011---";
FSR :="--------";
RPORTA :="-----";
RPORTB :="--------";
PCLATH :="---00000";
INTCON :="0-00000-";
OPTION :="11111111";
TRISA :="11111";
TRISB :="11111111";
w_reg :="00000000";
end if;
------------------Q1--------------------------------------
if(Q1'event and Q1 ='1') then

----------EXTERNAL PORTS .....output AT EVERY Q1....
for i in 0 to 4 loop
temp_rporta(i) := RPORTA(i);
end loop;
for i in 0 to 4 loop
if(TRISA(i) = '0')then
PORTA(i) <= temp_rporta(i);
else
PORTA(i) <='Z';
end if;
end loop;

for i in 0 to 7 loop
temp_rportb(i) := RPORTB(i);
end loop;

for i in 0 to 7 loop
if(TRISB(i) = '0')then
PORTB(i) <= temp_rportb(i);
else
PORTB(i) <='Z';
end if;
end loop;

end if;
..................................
..........
.......
--------------------------------------------------Q8---------------
if(Q8'event and Q8 ='1') then
STATUS(2 downto 0) := temp_z & temp_dc & temp_c;
for i in 0 to 4 loop
if(TRISA(i) ='1')then
RPORTA(i) :=PORTA(i);
end if;
end loop;
for i in 0 to 7 loop
if(TRISB(i) ='1')then
RPORTB(i) := PORTB(i);
end if;
end loop;
if((op_code = op_addwf)or(op_code = op_andwf)or(op_code = op_clrf)or
(op_code = op_comf)or(op_code = op_decf)or(op_code = op_decfsz)or
(op_code = op_incf)or(op_code = op_incfsz)or(op_code = op_iorwf)or
(op_code = op_movf)or(op_code = op_movwf)or(op_code = op_rlf)or
(op_code = op_rrf)or(op_code = op_subwf)or(op_code = op_swapf)or
(op_code = op_xorwf)or(op_code = op_clrw)) then
if(inst_reg(7)='0') then
w_reg := temp_result;
elsif(inst_reg(7)='1') then
if((temp_addr = R_0)or(temp_addr = R_1)or(temp_addr = R_2)or
(temp_addr = R_3)or(temp_addr = R_4)or(temp_addr = R_5)or
(temp_addr = R_6)or(temp_addr = R_7)or(temp_addr = R_8)or
(temp_addr = R_9)or(temp_addr = R_10)or(temp_addr = R_11)or
(temp_addr = R_12)or(temp_addr = R_13)or(temp_addr = R_14)or
(temp_addr = R_15)or(temp_addr = R_16)or(temp_addr = R_17)or
(temp_addr = R_18)or(temp_addr = R_19)or(temp_addr = R_20)or
(temp_addr = R_21)or(temp_addr = R_22)or(temp_addr = R_23)or
(temp_addr = R_24)or(temp_addr = R_25)or(temp_addr = R_26)or
(temp_addr = R_27)or(temp_addr = R_28)or(temp_addr = R_29)or
(temp_addr = R_30)or(temp_addr = R_31)or(temp_addr = R_32)or
(temp_addr = R_33)or(temp_addr = R_34)or(temp_addr = R_35))
then
wr <= '1';
data_out <= temp_result;
elsif ((STATUS(6 downto 5) & temp_addr) = R_INDF) then
wr <= '0';
INDF := temp_result ;
elsif ((STATUS(6 downto 5) & temp_addr) = R_TMR0) then
wr <= '0';
TMR0 := temp_result ;
elsif ((STATUS(6 downto 5) & temp_addr) = R_PCL) then
wr <= '0';
PCL := temp_result ;
elsif ((STATUS(6 downto 5) & temp_addr) = R_STATUS) then
wr <= '0';
STATUS(7 downto 3) := temp_result(7 downto 3) ;
elsif ((STATUS(6 downto 5) & temp_addr) = R_FSR) then
wr <= '0';
FSR := temp_result ;
elsif ((STATUS(6 downto 5) & temp_addr) = R_PORTA) then
wr <= '0';
RPORTA := temp_result(4 downto 0);
elsif ((STATUS(6 downto 5) & temp_addr) = R_PORTB) then
wr <= '0';
RPORTB := temp_result ;
elsif ((STATUS(6 downto 5) & temp_addr) = R_PCLATH) then
wr <= '0';
PCLATH := temp_result ;
elsif ((STATUS(6 downto 5) & temp_addr) = R_INTCON) then
wr <= '0';
INTCON := temp_result ;
elsif ((STATUS(6 downto 5) & temp_addr) = R_OPTION) then
wr <= '0';
OPTION := temp_result ;
elsif ((STATUS(6 downto 5) & temp_addr) = R_TRISA) then
wr <= '0';
TRISA := temp_result(4 downto 0) ;
elsif ((STATUS(6 downto 5) & temp_addr) = R_TRISB) then
wr <= '0';
TRISB := temp_result ;
elsif ((STATUS(6 downto 5) & temp_addr) = R_PCLB2) then
wr <= '0';
PCL := temp_result ;
elsif ((STATUS(6 downto 5) & temp_addr) = R_STATUSB2) then
wr <= '0';
STATUS(7 downto 3) := temp_result(7 downto 3) ;
elsif ((STATUS(6 downto 5) & temp_addr) = R_FSRB2) then
wr <= '0';
FSR := temp_result ;
elsif ((STATUS(6 downto 5) & temp_addr) = R_PCLATHB2) then
wr <= '0';
PCLATH := temp_result ;
elsif ((STATUS(6 downto 5) & temp_addr) = R_INTCONB2) then
wr <= '0';
INTCON := temp_result ;
elsif ((STATUS(6 downto 5) & temp_addr) = R_INDFB2) then
wr <= '0';
INDF := temp_result ;
end if;
end if;

elsif((op_code = op_addlw)or(op_code = op_andlw)or(op_code = op_iorlw) or
(op_code = op_movlw)or(op_code = op_sublw)or(op_code = op_xorlw)) then
w_reg := temp_result;
end if;
end if;
end process;
--------------------------------------
i am also including the files here.......

please help as soon as possible