L
Loppy
I am triying translate the C code:
int incrementarmodL(int input,int mod)
{
int salida;
salida = (input+2)%mod;
return salida;
}
to vhdl with REM operator
the code that I make is:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity inc2modL is
generic ( constant paso: std_logic_vector(7 downto 0):="00000010";
constant cero: std_logic_vector(7 downto 0):="00000000"
);
port ( entrada : in std_logic_vector(7 downto 0);
modulo : in std_logic_vector(7 downto 0);
reset : in std_logic;
salida : inout std_logic_vector(7 downto 0)
);
end inc2modL;
architecture comportamiento of inc2modL is
signal ent2 : std_logic_vector(7 downto 0);
signal v1: UNSIGNED(7 downto 0);
signal v2: UNSIGNED(7 downto 0);
signal v3: UNSIGNED(7 downto 0);
begin
process(entrada,modulo,reset)
begin
if reset='1' then
salida <= cero;
else
ent2 <= entrada or paso;
v1 <= UNSIGNED(ent2);
v2 <= UNSIGNED(modulo);
v3 <= v1 REM v2;
salida <= std_logic_vector(v3);
end if;
end process;
end comportamiento;
when I synthesize, the reports said:
ERROR:Xst:769 - C:/Almacen/Proyecto/Proyectos/pfc/inc2modl.vhd line 40:
Operator <INVALID OPERATOR> must have constant operands or first
operand must be power of 2
Anybody Can help me. Thanks
int incrementarmodL(int input,int mod)
{
int salida;
salida = (input+2)%mod;
return salida;
}
to vhdl with REM operator
the code that I make is:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity inc2modL is
generic ( constant paso: std_logic_vector(7 downto 0):="00000010";
constant cero: std_logic_vector(7 downto 0):="00000000"
);
port ( entrada : in std_logic_vector(7 downto 0);
modulo : in std_logic_vector(7 downto 0);
reset : in std_logic;
salida : inout std_logic_vector(7 downto 0)
);
end inc2modL;
architecture comportamiento of inc2modL is
signal ent2 : std_logic_vector(7 downto 0);
signal v1: UNSIGNED(7 downto 0);
signal v2: UNSIGNED(7 downto 0);
signal v3: UNSIGNED(7 downto 0);
begin
process(entrada,modulo,reset)
begin
if reset='1' then
salida <= cero;
else
ent2 <= entrada or paso;
v1 <= UNSIGNED(ent2);
v2 <= UNSIGNED(modulo);
v3 <= v1 REM v2;
salida <= std_logic_vector(v3);
end if;
end process;
end comportamiento;
when I synthesize, the reports said:
ERROR:Xst:769 - C:/Almacen/Proyecto/Proyectos/pfc/inc2modl.vhd line 40:
Operator <INVALID OPERATOR> must have constant operands or first
operand must be power of 2
Anybody Can help me. Thanks