ERROR:Xst:827 HELP Please!

[oppenheimer]

Hi All,

I'm one of the new members of this discussion platform and also beginner about VHDL. Nowadays, I'm trying to write a VHDL code to count from 0 to9 on a seven segmet display. I've XLINX CoolRunner-II CPLD board and I use WebPackISE 9.1i . But there is an error which I could not understand. Actually,I found an explanation about the error from XLINX webpage (which you can see below) but I couldn't pass the error. I have tried so many things on the code. If you help me about my problem, I' ll be grateful to you.

Thanks,
Oppenheimer.

The ERROR is:

ERROR:Xst:827 - "F:/CPLD_Designs/0-9_UpDown_Counter/Counter/Counter.vhd" line 41: Signal bcd cannot be synthesized, bad synchronous description.


The Explanation of ERROR from XLINX is:

A typical scenario for the above error message would be VHDL code similar to the following:

:
:
process (c, r) is begin
if r'event and r = '1' then
q <= '0';
elsif c'event and c = '1' then
q <= d;
end if;
end process;
:
:

or

:
:
process (c, r) is begin
if (r = '1' ) then
q <= '0';
if c'event and c = '1' then
q <= d;
end if;
end if;

end process;
:
:
Solution
Although your VHDL code might be syntactically correct, XST supports predefined templates for inferring various types of synchronous elements.

The synchronous element description is based on the 'event VHDL attribute. In order for XST to infer a synchronous element, the 'event VHDL attribute must be present in the topmost "IF" statement of your process. Furthermore, there should be no embedded 'event statements within a process. The following two examples illustrate this point:

Example 1:
:
:
synchronous_description : process (clk, reset) is begin
if clk'event and clk = '1' then -- topmost if statement
if reset = '1' then -- synchronous reset
q <= '0';
else
q <= d;
end if;
end if;
end process;
:
:

In the above example, there are no embedded 'event statements. In addition, the 'event statement is part of the topmost "IF" statement. Beneath the topmost "IF" statement is a description that will infer a synchronous reset. More embedded "IF" statements can be added to your design as necessary.

Example 2:

:
:
synchronous_description : process (clk, reset) is begin
if reset = '1' then -- asynchronous reset
q <= '0'; -- you can have embedded if statements if you need to
elsif clk'event and clk = '1' then -- still the topmost if statement
q <= d; -- you can put your case statements here or
end if; -- embed more if statements but not
end process; -- any more 'event statements
:
:

In the above example, there are no embedded 'event statements. In addition, the 'event statement is part of the topmost "IF" statement because it is associated with the "ELSIF" statement. More VHDL code can be inserted underneath the topmost "IF" statement as your design requires.

Templates for inferring registers, flip-flops, or memory can be found in Chapter 2 of the XST User Guide at:
http://www.xilinx.com/support/software_manuals.htm

Inference templates can also be found in the ISE Templates

And My Code is:

entity Counter is
Port ( Rst : in STD_LOGIC;
UpBtn : in STD_LOGIC;
DownBtn : in STD_LOGIC;
Data : out STD_LOGIC_VECTOR (6 downto 0):= "0111111" );
end Counter;

architecture Behavioral of Counter is
signal bcd: STD_LOGIC_VECTOR (3 downto 0) := "0000" ;
begin

process (UpBtn,DownBtn,Rst,bcd)
variable off: STD_LOGIC_VECTOR (6 downto 0):= "0000000" ;
variable zero: STD_LOGIC_VECTOR (6 downto 0):= "0111111" ;
begin
if Rst= '1' then
bcd<= "0000";
end if;

if UpBtn'event and UpBtn= '1' then
if (bcd= "1001") then
bcd<= "0000" ;
else
bcd<=bcd + 1;
end if;
end if;

if DownBtn'event and DownBtn= '1' then
if (bcd= "0000") then
Data<= off;
Data<= zero after 500 ms;
else
bcd<=bcd - 1;
end if;
end if;

case bcd is
when "0000" => Data<= "0111111";
when "0001" => Data<= "0000110";
when "0010" => Data<= "1011011";
when "0011" => Data<= "1001111";
when "0100" => Data<= "1100110";
when "0101" => Data<= "1101101";
when "0110" => Data<= "1111101";
when "0111" => Data<= "0000111";
when "1000" => Data<= "0111111";
when "1001" => Data<= "1101111";
when others => Data <= "1000000";
end case;

end process;


end Behavioral;

 

[jeppe]

process (c, r) is begin
if r'event and r = '1' then -- <<< BAD CODE
q <= '0';
elsif c'event and c = '1' then
q <= d;
end if;
end process;


well - your surely not allowed to use rising_edge at both the reset and the clk.

http://www.jjmk.dk/MMMI/Exercises/05_Counters_Shreg/No2_MultipleClocks/exer5_2.htm

 

[oppenheimer]

Thank you very much jeppe! The document which you suggested was very very usefull. I got what is wrong and learnt lots of things.

Oppenheimer.