Errors with model sim

[srinukasam]

hello to all

i wrote 3 procedures to read the content of file ( for stimulation data).
and i described these in package.
when i complie its showing no errors, but when i start simulation its
showing these errors and pointing the procedure line of code.

# ** Fatal: (vsim-3421) Value 10 for i is out of range 9 downto 0.
# Time: 0 ns Iteration: 0 Process: /varification/test File:
/disk/users2/kasam/hds_projects/Controller/controller_v1/hdl/varification_varification_str.vhd
# Fatal error at
/disk/users2/kasam/hds_projects/Controller/controller_v1/hdl/c_pak_pkg.vhd
line 103
#

verification is my test bench.
IS THERE ANY error in my procedure..
please help me.
thank to all
below is realted code to this problem..



PACKAGE C_PKG::
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use std.textio.all;

PACKAGE c_pak IS
constant ictrl_w1 : integer := 8; -- control signal width
constant ictrl_w2 : integer := 4;
constant ictrl_w3 : integer := 5;
constant ictrl_w4 : integer := 8;

function conv_integer1(a:bit_vector(ictrl_w1-1 downto 0)) return
integer;
function conv_integer2(a:bit_vector(ictrl_w2-1 downto 0)) return
integer;
function conv_integer3(a:bit_vector(ictrl_w3-1 downto 0)) return
integer;
function conv_integer4(a:bit_vector(ictrl_w4-1 downto 0)) return
integer;
--function int_to_vect(size:integer; val:integer) return bit_vector;
procedure readbitstring (variable patternline: in line; column: inout
positive;
variable bitstring: out bit_vector);

--procedure readbit (variable patternline: in line; column: inout
positive; variable bit: out bit);

procedure readbit (variable patternline: in line; column: inout
positive; variable bit1: out bit);
--procedure readpatternline(file patternfile:text;
string1,string2,string3,string4,string5,string6,
--
string7,string8,string9,string10,string11,string12,string13,string14ut
bit_vector);
procedure readpatternline(file patternfile:text;
string2,string3,string4,string5,string6,
string7ut bit;
string1,string8,string9,string10,string11,string12,string13,string14ut
bit_vector);

END c_pak;


package body c_pak is

function conv_integer1(a :bit_vector(ictrl_w1-1 downto 0)) return
integer is
variable result :integer:=0;
variable int_res : integer:=0;
begin
for i in 0 to ictrl_w1-1 loop
if a(i) = '1' then
int_res:=2**i;
--int_res := unsigned(a(i))*(2**i);
result := result+int_res;
end if;
end loop;
return result;
end conv_integer1;

function conv_integer2(a :bit_vector(ictrl_w2-1 downto 0)) return
integer is
variable result :integer:=0;
variable int_res : integer:=0;
begin
for i in 0 to ictrl_w2-1 loop
if a(i) = '1' then
int_res:=2**i;
--int_res := unsigned(a(i))*(2**i);
result := result+int_res;
end if;
end loop;
return result;
end conv_integer2;

function conv_integer3(a :bit_vector(ictrl_w3-1 downto 0)) return
integer is
variable result :integer:=0;
variable int_res : integer:=0;
begin
for i in 0 to ictrl_w3-1 loop
if a(i) = '1' then
int_res:=2**i;
--int_res := unsigned(a(i))*(2**i);
result := result+int_res;
end if;
end loop;
return result;
end conv_integer3;

function conv_integer4(a :bit_vector(ictrl_w4-1 downto 0)) return
integer is
variable result :integer:=0;
variable int_res : integer:=0;
begin
for i in 0 to ictrl_w4-1 loop
if a(i) = '1' then
int_res:=2**i;
--int_res := unsigned(a(i))*(2**i);
result := result+int_res;
end if;
end loop;
return result;
end conv_integer4;

procedure readbitstring (variable patternline: in line; column:
inout positive; variable bitstring: out bit_vector) is
variable i :integer:=1;
begin
while patternline(column)/= ' ' loop
case patternline(column) is
when '1'=> bitstring(i):='1';
when others => bitstring(i):='0';
end case;
column:=column+1;
i:=i+1;
end loop;
column:=column+1;
end procedure;

procedure readbit (variable patternline: in line; column: inout
positive; variable bit1: out bit) is
--variable i :natural:=1;
begin
while patternline(column)/= ' ' loop
case patternline(column) is
when '1'=> bit1:='1';
when others => bit1:='0';
end case;
--column:=column+1;
--i:=i+1;
end loop;
column:=column+1;
end procedure;

procedure readpatternline(file patternfile:text;
string2,string3,string4,string5,string6,
string7ut bit;
string1,string8,string9,string10,string11,string12,string13,string14ut
bit_vector) is

variable patternline: line;
variable column:integer;
begin
readline(patternfile, patternline);
column:=1;
readbitstring(patternline, column, string1);
readbit(patternline, column, string2);
readbit(patternline, column, string3);
readbit(patternline, column, string4);
readbit(patternline, column, string5);
readbit(patternline, column, string6);
readbit(patternline, column, string7);
readbitstring(patternline, column, string8);
readbitstring(patternline, column, string9);
readbitstring(patternline, column, string10);
readbitstring(patternline, column, string11);
readbitstring(patternline, column, string12);
readbitstring(patternline, column, string13);
readbitstring(patternline, column, string14);


end procedure;
end c_pak;

VERIFICATION FILE::

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use std.textio.all;
use work.c_pak.all;

ENTITY varification IS
generic ( input_w :integer :=10; --input signal width
ictrl_w :integer :=4; -- individual control signal
width
tctrl_w : integer :=20; -- total control signal width--mem
out
no_out,no_ctrl :integer :=5; -- no of output
signals(r),no.of control signals (V)
addr_width_m: integer:=8;
data_width_m: integer :=20;
addr_width_nead: integer:=5;
data_width_nead: integer :=40;
addr_width_nest: integer:=5;
data_width_nest: integer :=40;

state_w :integer :=8;
tstate_w:integer:=40;
no_ns:integer:=5);
END ENTITY varification;

--
ARCHITECTURE varification_str OF varification IS



component cdesign

generic ( input_w :integer :=10; --input signal width
ictrl_w :integer :=4; -- individual control signal
width
tctrl_w : integer :=20; -- total control signal width--mem
out
no_out,no_ctrl :integer :=5; -- no of output
signals(r),no.of control signals (V)
addr_width_m: integer:=8;
data_width_m: integer :=20;
addr_width_nead: integer:=5;
data_width_nead: integer :=40;
addr_width_nest: integer:=5;
data_width_nest: integer :=40;

state_w :integer :=8;
tstate_w:integer:=40;
no_ns:integer:=5);
port( input:in bit_vector(input_w-1 downto 0);
clk:in bit;
r_clk:in bit;
we_m,we_nead,we_nest,re_m,re_nead,re_nest:in bit;
w_addr_nead,w_addr_nest:in bit_vector(addr_width_nead-1 downto
0);
w_addr_m:in bit_vector(addr_width_m-1 downto 0);

data_in_m:in bit_vector(data_width_m-1 downto 0);
data_in_nead,data_in_nest:in bit_vector(data_width_nead-1 downto
0);

state_out_oput bit_vector(state_w-1 downto 0));

end component;

signal clk:bit:='0';
signal r_clk:bit:='0';
signal input: bit_vector(input_w-1 downto 0);
signal we_m,we_nead,we_nest,re_m,re_nead,re_nest: bit;
signal w_addr_nead,w_addr_nest: bit_vector(addr_width_nead-1 downto
0);
signal w_addr_m: bit_vector(addr_width_m-1 downto 0);
signal data_in_m: bit_vector(data_width_m-1 downto 0);
signal data_in_nead,data_in_nest: bit_vector(data_width_nead-1 downto
0);
signal state_out_op: bit_vector(state_w-1 downto 0);

BEGIN

clk<=not clk after 5 ns;

mut :cdesign port
map(input,clk,r_clk,we_m,we_nead,we_nest,re_m,re_nead,re_nest,w_addr_nead,w_addr_nest,

w_addr_m,data_in_m,data_in_nead,data_in_nest,state_out_op);

testrocess
constant iterations: integer:=2;
file patternfile: text open read_mode is
"/disk/users2/kasam/hds_projects/Controller/controller_v1/hdl/test_sig.dat";

variable bitstring1: bit_vector (input_w-1 downto 0);
variable bitstring2: bit;
variable bitstring3: bit;
variable bitstring4: bit;
variable bitstring5: bit;
variable bitstring6: bit;
variable bitstring7: bit;
variable bitstring8: bit_vector (addr_width_m-1 downto 0);
variable bitstring9: bit_vector (addr_width_nead-1 downto 0);
variable bitstring10: bit_vector (addr_width_nead-1 downto 0);
variable bitstring11: bit_vector (data_width_nead-1 downto 0);
variable bitstring12: bit_vector (data_width_nead-1 downto 0);
variable bitstring13: bit_vector (data_width_m-1 downto 0);
variable bitstring14: bit_vector (state_w-1 downto 0);
variable result : bit_vector (state_w-1 downto 0);

begin
for i in 1 to iterations loop


readpatternline(patternfile,bitstring2,bitstring3,bitstring4,bitstring5,bitstring6,bitstring7,bitstring1,
bitstring8,bitstring9,bitstring10,bitstring11,bitstring12,bitstring13,bitstring14);

input<=bitstring1;
we_m<=bitstring2;
we_nead<=bitstring3;
we_nest<=bitstring4;
re_m<=bitstring5;
re_nead<=bitstring6;
re_nest<=bitstring7;
w_addr_m<=bitstring8;
w_addr_nead<=bitstring9;
w_addr_nest<=bitstring10;
data_in_m<=bitstring11;
data_in_nead<=bitstring12;
data_in_nest<=bitstring13;
result:=bitstring14;

--wait for 36 ns;
assert(result=state_out_op) report "error in desin" severity error;



wait;
end loop;
end process;

END ARCHITECTURE varification_str;

CONTENT OF TEST_SIG:::
--1 ST LINE
0100000000 1 1 1 1 1 1 00000 00000 00000000 00000000000000000000
0000000000000001000000100000001100000100
0000000100000010000000110000010000000101 00000001
--2ND LINE
0100000001 1 1 1 1 1 1 00000 00000 00000000 00000000000000000000
0000000000000001000000100000001100000100
0000000100000010000000110000010000000101 00000010

 

[Lars Wehmeyer]

# ** Fatal: (vsim-3421) Value 10 for i is out of range 9 downto 0.
# Time: 0 ns Iteration: 0 Process: /varification/test File:
/disk/users2/kasam/hds_projects/Controller/controller_v1/hdl/varification_varification_str.vhd
# Fatal error at
/disk/users2/kasam/hds_projects/Controller/controller_v1/hdl/c_pak_pkg.vhd
line 103
#

It would help to isolate and show line 103 of your package. There
is a problem with the index range of an expression: the declaration
of the vector (?) goes from 9 downto 0, and your index expression
in line 103 takes the value 10. HTH

Lars

P.S.: Sorry for being too lazy to count lines in your code...

 

[srinukasam]

hello to all

i wrote 3 procedures to read the content of file ( for stimulation data).
and i described these in package.
when i complie its showing no errors, but when i start simulation its
showing these errors and pointing the procedure line of code.

# ** Fatal: (vsim-3421) Value 10 for i is out of range 9 downto 0.
# Time: 0 ns Iteration: 0 Process: /varification/test File:
/disk/users2/kasam/hds_projects/Controller/controller_v1/hdl/varification_varification_str.vhd
# Fatal error at
/disk/users2/kasam/hds_projects/Controller/controller_v1/hdl/c_pak_pkg.vhd
line 103
#

verification is my test bench.
IS THERE ANY error in my procedure..
please help me.
thank to all
below is realted code to this problem..



PACKAGE C_PKG::
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use std.textio.all;

PACKAGE c_pak IS
constant ictrl_w1 : integer := 8; -- control signal width
constant ictrl_w2 : integer := 4;
constant ictrl_w3 : integer := 5;
constant ictrl_w4 : integer := 8;

function conv_integer1(a:bit_vector(ictrl_w1-1 downto 0)) return
integer;
function conv_integer2(a:bit_vector(ictrl_w2-1 downto 0)) return
integer;
function conv_integer3(a:bit_vector(ictrl_w3-1 downto 0)) return
integer;
function conv_integer4(a:bit_vector(ictrl_w4-1 downto 0)) return
integer;
--function int_to_vect(size:integer; val:integer) return bit_vector;
procedure readbitstring (variable patternline: in line; column: inout
positive;
variable bitstring: out bit_vector);

--procedure readbit (variable patternline: in line; column: inout
positive; variable bit: out bit);

procedure readbit (variable patternline: in line; column: inout
positive; variable bit1: out bit);
--procedure readpatternline(file patternfile:text;
string1,string2,string3,string4,string5,string6,
--
string7,string8,string9,string10,string11,string12,string13,string14ut
bit_vector);
procedure readpatternline(file patternfile:text;
string2,string3,string4,string5,string6,
string7ut bit;
string1,string8,string9,string10,string11,string12,string13,string14ut
bit_vector);

END c_pak;


package body c_pak is

function conv_integer1(a :bit_vector(ictrl_w1-1 downto 0)) return
integer is
variable result :integer:=0;
variable int_res : integer:=0;
begin
for i in 0 to ictrl_w1-1 loop
if a(i) = '1' then
int_res:=2**i;
--int_res := unsigned(a(i))*(2**i);
result := result+int_res;
end if;
end loop;
return result;
end conv_integer1;

function conv_integer2(a :bit_vector(ictrl_w2-1 downto 0)) return
integer is
variable result :integer:=0;
variable int_res : integer:=0;
begin
for i in 0 to ictrl_w2-1 loop
if a(i) = '1' then
int_res:=2**i;
--int_res := unsigned(a(i))*(2**i);
result := result+int_res;
end if;
end loop;
return result;
end conv_integer2;

function conv_integer3(a :bit_vector(ictrl_w3-1 downto 0)) return
integer is
variable result :integer:=0;
variable int_res : integer:=0;
begin
for i in 0 to ictrl_w3-1 loop
if a(i) = '1' then
int_res:=2**i;
--int_res := unsigned(a(i))*(2**i);
result := result+int_res;
end if;
end loop;
return result;
end conv_integer3;

function conv_integer4(a :bit_vector(ictrl_w4-1 downto 0)) return
integer is
variable result :integer:=0;
variable int_res : integer:=0;
begin
for i in 0 to ictrl_w4-1 loop
if a(i) = '1' then
int_res:=2**i;
--int_res := unsigned(a(i))*(2**i);
result := result+int_res;
end if;
end loop;
return result;
end conv_integer4;

procedure readbitstring (variable patternline: in line; column:
inout positive; variable bitstring: out bit_vector) is
variable i :integer:=1;
begin
while patternline(column)/= ' ' loop
case patternline(column) is
when '1'=> bitstring(i):='1';
when others => bitstring(i):='0'; ----THIS IS THE 103 LINE
S´HOWING ERROR::
end case;
column:=column+1;
i:=i+1;
end loop;
column:=column+1;
end procedure;

procedure readbit (variable patternline: in line; column: inout
positive; variable bit1: out bit) is
--variable i :natural:=1;
begin
while patternline(column)/= ' ' loop
case patternline(column) is
when '1'=> bit1:='1';
when others => bit1:='0';
end case;
--column:=column+1;
--i:=i+1;
end loop;
column:=column+1;
end procedure;

procedure readpatternline(file patternfile:text;
string2,string3,string4,string5,string6,
string7ut bit;
string1,string8,string9,string10,string11,string12,string13,string14ut
bit_vector) is

variable patternline: line;
variable column:integer;
begin
readline(patternfile, patternline);
column:=1;
readbitstring(patternline, column, string1);
readbit(patternline, column, string2);
readbit(patternline, column, string3);
readbit(patternline, column, string4);
readbit(patternline, column, string5);
readbit(patternline, column, string6);
readbit(patternline, column, string7);
readbitstring(patternline, column, string8);
readbitstring(patternline, column, string9);
readbitstring(patternline, column, string10);
readbitstring(patternline, column, string11);
readbitstring(patternline, column, string12);
readbitstring(patternline, column, string13);
readbitstring(patternline, column, string14);


end procedure;
end c_pak;

VERIFICATION FILE::

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use std.textio.all;
use work.c_pak.all;

ENTITY varification IS
generic ( input_w :integer :=10; --input signal width
ictrl_w :integer :=4; -- individual control signal
width
tctrl_w : integer :=20; -- total control signal
width--mem
out
no_out,no_ctrl :integer :=5; -- no of output
signals(r),no.of control signals (V)
addr_width_m: integer:=8;
data_width_m: integer :=20;
addr_width_nead: integer:=5;
data_width_nead: integer :=40;
addr_width_nest: integer:=5;
data_width_nest: integer :=40;

state_w :integer :=8;
tstate_w:integer:=40;
no_ns:integer:=5);
END ENTITY varification;

--
ARCHITECTURE varification_str OF varification IS



component cdesign

generic ( input_w :integer :=10; --input signal width
ictrl_w :integer :=4; -- individual control signal
width
tctrl_w : integer :=20; -- total control signal
width--mem
out
no_out,no_ctrl :integer :=5; -- no of output
signals(r),no.of control signals (V)
addr_width_m: integer:=8;
data_width_m: integer :=20;
addr_width_nead: integer:=5;
data_width_nead: integer :=40;
addr_width_nest: integer:=5;
data_width_nest: integer :=40;

state_w :integer :=8;
tstate_w:integer:=40;
no_ns:integer:=5);
port( input:in bit_vector(input_w-1 downto 0);
clk:in bit;
r_clk:in bit;
we_m,we_nead,we_nest,re_m,re_nead,re_nest:in bit;
w_addr_nead,w_addr_nest:in bit_vector(addr_width_nead-1 downto
0);
w_addr_m:in bit_vector(addr_width_m-1 downto 0);

data_in_m:in bit_vector(data_width_m-1 downto 0);
data_in_nead,data_in_nest:in bit_vector(data_width_nead-1 downto
0);

state_out_oput bit_vector(state_w-1 downto 0));

end component;

signal clk:bit:='0';
signal r_clk:bit:='0';
signal input: bit_vector(input_w-1 downto 0);
signal we_m,we_nead,we_nest,re_m,re_nead,re_nest: bit;
signal w_addr_nead,w_addr_nest: bit_vector(addr_width_nead-1 downto
0);
signal w_addr_m: bit_vector(addr_width_m-1 downto 0);
signal data_in_m: bit_vector(data_width_m-1 downto 0);
signal data_in_nead,data_in_nest: bit_vector(data_width_nead-1 downto
0);
signal state_out_op: bit_vector(state_w-1 downto 0);

BEGIN

clk<=not clk after 5 ns;

mut :cdesign port
map(input,clk,r_clk,we_m,we_nead,we_nest,re_m,re_nead,re_nest,w_addr_nead,w_addr_nest,

w_addr_m,data_in_m,data_in_nead,data_in_nest,state_out_op);

testrocess
constant iterations: integer:=2;
file patternfile: text open read_mode is
"/disk/users2/kasam/hds_projects/Controller/controller_v1/hdl/test_sig.dat";

variable bitstring1: bit_vector (input_w-1 downto 0);
variable bitstring2: bit;
variable bitstring3: bit;
variable bitstring4: bit;
variable bitstring5: bit;
variable bitstring6: bit;
variable bitstring7: bit;
variable bitstring8: bit_vector (addr_width_m-1 downto 0);
variable bitstring9: bit_vector (addr_width_nead-1 downto 0);
variable bitstring10: bit_vector (addr_width_nead-1 downto 0);
variable bitstring11: bit_vector (data_width_nead-1 downto 0);
variable bitstring12: bit_vector (data_width_nead-1 downto 0);
variable bitstring13: bit_vector (data_width_m-1 downto 0);
variable bitstring14: bit_vector (state_w-1 downto 0);
variable result : bit_vector (state_w-1 downto 0);

begin
for i in 1 to iterations loop


readpatternline(patternfile,bitstring2,bitstring3,bitstring4,bitstring5,bitstring6,bitstring7,bitstring1,
bitstring8,bitstring9,bitstring10,bitstring11,bitstring12,bitstring13,bitstring14);

input<=bitstring1;
we_m<=bitstring2;
we_nead<=bitstring3;
we_nest<=bitstring4;
re_m<=bitstring5;
re_nead<=bitstring6;
re_nest<=bitstring7;
w_addr_m<=bitstring8;
w_addr_nead<=bitstring9;
w_addr_nest<=bitstring10;
data_in_m<=bitstring11;
data_in_nead<=bitstring12;
data_in_nest<=bitstring13;
result:=bitstring14;

--wait for 36 ns;
assert(result=state_out_op) report "error in desin" severity error;



wait;
end loop;
end process;

END ARCHITECTURE varification_str;

CONTENT OF TEST_SIG:::
--1 ST LINE
0100000000 1 1 1 1 1 1 00000 00000 00000000 00000000000000000000
0000000000000001000000100000001100000100
0000000100000010000000110000010000000101 00000001
--2ND LINE
0100000001 1 1 1 1 1 1 00000 00000 00000000 00000000000000000000
0000000000000001000000100000001100000100
0000000100000010000000110000010000000101 00000010

 

[Jonathan Bromley]

P.S.: Sorry for being too lazy to count lines in your code...

I hardly think you need to apologise, Lars - even if you had
your tongue in your cheek at the time. Is anyone else
offended to the same degree that I am by someone who is so
idle in their problem-solving that they simply dump the whole
of a poorly commented mess of code on the newsgroup, without
making any effort to trace or isolate the problem?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:[email protected]
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[srinukasam]

hello
thank you for your comment..
i checked my self for that problem around 1 day.. and i checked all my
variable in design for any violation of generics..but no varible is
violating..
and why i gave all my code is just to refer..if some one wants to give a
answer to my problem ( I WANT TO PROVIDE FULL INFO) thats all..
bye

 

[Jonathan Bromley]

i checked my self for that problem around 1 day..

And the outcome of that day's work was.... an error
diagnostic and the same source code you started with?
What possibilities did you consider, investigate and
eliminate?

and i checked all my
variable in design for any violation of generics..but no varible is
violating...

The simulator seems to disagree.

and why i gave all my code is just to refer..if some one wants to give a
answer to my problem

But you did not even take the trouble to point out which line in
the mass of code is the line that gave rise to the error.

Here's what you must do. It's known as DEBUGGING...

- Determine which index variable is giving rise to the error.
- Identify every place where that variable is updated,
and look for scenarios where it could be given the
wrong value. Typically this will be a loop that
runs one step too far, or an end-of-loop test like
while (i > i_max) loop...
where i is of a subtype constrained to be <= i_max.
- If that static analysis of the code doesn't help, then
instrument the code by displaying the value of the
offending variable at various places. In file reading
code like yours, it's also a good idea to display
each line of the file as you read it, so that you can see
what kind of input text causes the problem and what
works OK. Then run the code again, and use the new
information to get you closer to the answer.
- Remove parts of the problem until you have isolated
just the part that causes trouble. For example, if
you are reading text from a file, change your program
so that it reads only one line of text. Does that work?
When you have stripped the problem to its bare essentials
and you still have the failure, then you will have a
small piece of code and it will be OK to ask others
to look at it.

Debugging is never trivially easy, but if you start with
intelligent attempts like I've outlined, you will soon
see other opportunities to add tests, write debugging
output or various other tricks to help find the problem.
Don't expect the answer to be apparent immediately - you
will need to act like a detective, making inspired guesses
at what's happening and then eliminating those guesses
as the evidence proves them to be false. Finally, one
of the guesses will lead you to the right answer.
Skilled debuggers make use of all the evidence they
can find to push their guesses in the right direction.

So now I've given you 100% more help than I originally
intended. Whatever you do, please DON'T simply pick up
the whole problem and dump it on someone else's doorstep.

( I WANT TO PROVIDE FULL INFO) thats all..

You provided almost no *information*; you merely provided
a large and incoherent heap of *data*.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:[email protected]
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Mike Treseler]

i wrote 3 procedures to read the content of file ( for stimulation data).
and i described these in package.

Note that many of the functions in your package
are covered by the standard and well tested
ieee.numeric_std library. Consider learning
and using it.

when i complie its showing no errors, but when i start simulation its
showing these errors and pointing the procedure line of code.

This is the most common run-time error
in any language, an array subscript is out of bounds.

# ** Fatal: (vsim-3421) Value 10 for i is out of range 9 downto 0.
# Time: 0 ns Iteration: 0 Process: /varification/test File:

/disk/users2/kasam/hds_projects/Controller/controller_v1/hdl/c_pak_pkg.vhd
line 103

My first debug step would be, go to line 103, figure out which
variable is implicated and adjust its declaration range.
This may fix the problem or cause another.
But it might give you a clue.

-- Mike Treseler

 

[Srinivasan Venkataramanan]

Hi Srinu,
Jonathan has cleanly described a process called "structured problem
solving" as it applies to your current problem. Don't get offended, many of
the forum members are full time engineers having specific targets to meet -
they don't have time (nor any ROI) to go thro' 100s of lines of others'
code - for no return. We are willing to help, but provided you invest your
time in the correct way - just putting one day (or more) is not enough - how
effective you are counts (as they say it: Results count, reasons don't). In
this specific case, your simulator indicated:

# ** Fatal: (vsim-3421) Value 10 for i is out of range 9 downto 0.

^^^^^^^^^^^^^^

Look where "i" is used as loop/running variable. Which vector(s) do you have
in YOUR code (you should know it the best anyway) of length 10 (9 downto 0).

# Fatal error at
/disk/users2/kasam/hds_projects/Controller/controller_v1/hdl/c_pak_pkg.vhd
line 103

See what's in your line no. 103 - if you are still stuck, try and isolate
this line 103, relevant "i", signal causing the issue etc. and do line
stepping in your simulator. (Not the most efficient way, but a way to learn
things).

Most importantly - as Mike pointed out, try and see if you can use
numeric_std functions - sounds to me like you don't need these those many
conversion functions.

Also, your choice of variable/signal names is undesirable - "string1,
string2" etc. for bit_vector?

Good luck Srinu!
Sri

--
Srinivasan Venkataramanan
Co-Author: SystemVerilog Assertions Handbook, http://www.abv-sva.org
Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition.
http://www.noveldv.com
I own my words and not my employer, unless specifically mentioned

 

[Andy Peters]

It would help to isolate and show line 103 of your package. There
is a problem with the index range of an expression: the declaration
of the vector (?) goes from 9 downto 0, and your index expression
in line 103 takes the value 10. HTH

Lars

P.S.: Sorry for being too lazy to count lines in your code...

It looks like homework to me. We need to give the prof a big fat F.

-a