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Hi.
Do someone have experience of working with the "new" package IEEE.Float_Pkg, proposed for VHDL 2006? Does it consume lots of logic compared to std_logic_vectors (based on the same number of bits)? The main operations I will use is multiplications and additions.
Will do some tests but am curious of your experience.
Thanks
Martin
Do someone have experience of working with the "new" package IEEE.Float_Pkg, proposed for VHDL 2006? Does it consume lots of logic compared to std_logic_vectors (based on the same number of bits)? The main operations I will use is multiplications and additions.
Will do some tests but am curious of your experience.
Thanks
Martin