explanation

M

Mariusz

Hello. I'm new to VHDL. Could someone explain me what does the following
code snippet does? I completely don't get what is the generate clause for. I
wanted to look at the help file but help in my webpack seems to be broken
and it says that there is no such topic :(
This is very important to me to understand this code, becouse i have to use
it in my own program. And it's little difficulf for me to do this without
understanding...


TheBRAM: for i in DataIn'range generate
signal ToLow, ToHigh : std_logic;
type TData is array (DataIn'range) of std_logic_vector(0 downto 0);
signal DataInArray : TData;
signal DataOutArray : TData;
signal FullAddress : std_logic_vector(11 downto 0);
attribute init_00 : string;
attribute init_00 of OneRAM : label is
"FFFF" & "FFFF" & "FFFF" & "FFFF" & "FFFF" & "FFFF" & "FFFF" & "FFFF" &
"FFFF" & "FFFF" & "FFFF" & "FFFF" & "FFFF" & "FFFF" & "FFFF" & "FFFF"
;
begin
ToLow <= '0';
ToHigh <= '1';
DataInArray(i)(0) <= DataIn(i);
DataOut(i) <= DataOutArray(i)(0);

DoFullAddress: for j in FullAddress'range generate
AssignAddress: if (j >= Address'low) and (j <= Address'high) generate
FullAddress(j) <= Address(j);
end generate;
AssignZero: if (j < Address'low) or (j > Address'high) generate
FullAddress(j) <= '0';
end generate;
end generate DoFullAddress;

OneRAM: RAMB4_S1 port map(
WE=>WrEn,
EN => ToHigh,
RST => ToLow,
Clk => Clk,
Addr => FullAddress,
DI=>DataInArray(i),
DO=> DataOutArray(i)
);
end generate TheBRAM;
 

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