exponent in vhdl

[cLaRe]

hi i was wondering how to exponent if i hav the input declared as std_logic_vector??

 

[jeppe]

Depends on your plans:

For simulation use the type real
For synthesizing check this site:
http://tima-cmp.imag.fr/~guyot/Cours/Oparithm/english/Fonctio.htm

Your welcome
Jeppe

 

[cLaRe]

Depends on your plans:

For simulation use the type real
For synthesizing check this site:
http://tima-cmp.imag.fr/~guyot/Cours/Oparithm/english/Fonctio.htm

Your welcome
Jeppe

can u explain further ??

 

[jeppe]

Well I never realy "had this problem" but I guess you must consult some math-books in order to understand the algorithm.

Besides - I gave you a wrong link - sorry:
http://tima-cmp.imag.fr/~guyot/Cours/Oparithm/english/Flottan.htm
But this one even harder to understand I believe.

Jeppe

 

[cLaRe]

thanks alot..i will try to read up !