factors needed to choose VHDL or verilog

[srinivas.hyd]

i am fairly good VHDL designer, and have a superficial overview of verilog. i have read many articles through google search engine about comparison between VHDL and verilog. but most of them i felt were biased. i couldn't get any link which illustrates the advantages and disadvantages of VHDL over Verilog. please help me find the present status of these two HDLs. also, i heard that VITAL is used as a cross-link to verilog primitives to provide VHDL the edge for gate level modeling, is that true?. in using mixed HDL design of both VHDL and verilog how can we get maximum benefit, i.e, what are the areas we should prefer using VHDL or Verilog and vice-versa.
please provide the links that illustrate the factors needed to chose one of them