fast ISE bitfile making!

[vbehravan]

hi all.
whenever I change the VHDL code(only a little change like replacing a<=b with a<=not(b) ), ISE starts to do all sequencess(synthesize,translate,map,Place&Route) from first for all design and so takes several minuits to make bit file,while i have changed only a little portion of hardware(VHDL code).

is there any solution to accelerate this process when changes in the code are very little?

I mean is there any way to force ISE to only Place&Route the changed section?

regards.

 

[scottcarl]

Sorry about that, but no matter how small the code change is to the VHDL code, everything has to run again. There are ways to do partial recompiles where you lock down part of the code but it sometimes makes timing closure difficult to obtain and it's difficult to figure out how to do it.

 

[quantum_dot]

Fast ISE bitfile making !

Well, now ISE 9.1 supports a feature where you can recompile a particular block/partition of the complete project, without disturbing the rest of the floor planning or timing closure issues. And this way the bitfile generation becomes really fast. Check out the new features of Xilinx ISE9.1
:driver: