Z
Zyd
Hello all,
I am doing project on Memory built in self test. I need anyone here to
help me to check my faulty SRAM I write in VHDL. I need this to
verify that my MBST controller can detect such faults.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sram_ut2 is
generic(ADD_BUS : integer := 3;
DATA_BUS : integer := 7);
port (CLOCK : in std_logic;
CE : in std_logic;
WE : in std_logic;
RD : in std_logic;
ADDRESS : in std_logic_vector(ADD_BUS downto 0);
DATAIN : in std_logic_vector(DATA_BUS downto 0);
DATAOUT : out std_logic_vector(DATA_BUS downto 0));
end sram_ut2;
architecture Behavioral of sram_ut2 is
type ram_type is array (0 to (2**(ADD_BUS + 1)) - 1) of
std_logic_vector(DATA_BUS downto 0);
signal RAM : ram_type;
signal A : std_logic_vector(DATA_BUS downto 0);
begin
write_read: process (CE, CLOCK, DATAIN, ADDRESS)
begin
if (CE = '1') then
for i in 0 to (2**(ADD_BUS + 1 ) - 1) loop
RAM(i) <= (others => '0');
end loop;
DATAOUT <= (others => 'Z');
elsif (CLOCK'event and CLOCK = '1') then
if (WE = '1') then
--Introducing stuck at 0 fault at bit 0 of location 0
if (ADDRESS = "0000") then
RAM(conv_integer(ADDRESS)) <= (DATAIN and "11111110");
--Introducing stuck at 1 fault at bit 7 of location 1
elsif (ADDRESS = "0001") then
RAM(conv_integer(ADDRESS)) <= (DATAIN or "10000000");
--Introducing 0 to 1 transition fault in bit 5 of location 2
elsif (ADDRESS = "0010") then
if ((RAM(conv_integer(ADDRESS))
and "00100000") = "00000000") then
RAM(conv_integer(ADDRESS)) <= DATAIN and "11011111";
else
RAM(conv_integer(ADDRESS)) <= DATAIN;
end if;
--Introducing 1 to 0 transition fault in bit 2 of location 3
elsif (ADDRESS = "0011") then
if ((RAM(conv_integer(ADDRESS))
and "00000100") = "00000100") then
RAM(conv_integer(ADDRESS)) <= DATAIN or "00000100";
else
RAM(conv_integer(ADDRESS)) <= DATAIN;
end if;
--Introducing inversion coupling fault between cells ofdifferent
--bytes(4 and 5)
--A transition in bit 6 of loc. 4 causes bit 6 of location 5 to
--be inverted
elsif (ADDRESS = "0100") then
if (ADDRESS = "0100") then
RAM(conv_integer(ADDRESS)) <= DATAIN ;
if (RAM(conv_integer(ADDRESS)) = "11111111") then
RAM(5) <= RAM(5) or "01000000";
elsif (RAM(conv_integer(ADDRESS)) = "00000000") then
RAM(5) <= RAM(5) and "10111111";
end if;
else
RAM(conv_integer(ADDRESS)) <= DATAIN;
end if;
-- Introducing ADDRESS decoder faults
-- Fault 1+2: ADDRESS of 8, no location is accessed
elsif (ADDRESS = "1000") then
null;
-- Fault 3+4: ADDRESS of 9 locations 9 and 15
-- are accessed simultaneously
-- Location 15 is also accessed when ADDRESS 15 is applied
elsif (ADDRESS = "1001") then
RAM(conv_integer(ADDRESS)) <= DATAIN;
RAM(conv_integer(15)) <= DATAIN;
--Fault 1+3: ADDRESS of 10, locations 10 and 14
-- are accessed, but location 14 is not accessed when
-- ADDRESS 14 is applied
elsif (ADDRESS = "1010") then
if (ADDRESS = "1010") then
RAM(conv_integer(ADDRESS)) <= DATAIN;
RAM(conv_integer(ADDRESS + 4)) <= DATAIN;
elsif (ADDRESS = "1110") then
null;
end if;
--Fault 2+4: With ADDRESS of 11 or 13, location 13 is accessed,
-- so location 11 is never accessed
elsif (ADDRESS = "1011" or ADDRESS = "1101") then
RAM(13) <= DATAIN;
--Misdirected address fault (decoder fault)
--With ADDRESS 12, location 7 is accessed not location 12
--when ADDRESS 7, no location is access
elsif (ADDRESS = "1100") then
RAM(7) <= DATAIN;
else
RAM(conv_integer(ADDRESS)) <= DATAIN;
end if;
elsif (RD = '1') then
DATAOUT <= RAM(conv_integer(ADDRESS));
end if;
end if;
end process;
end Behavioral;
I am doing project on Memory built in self test. I need anyone here to
help me to check my faulty SRAM I write in VHDL. I need this to
verify that my MBST controller can detect such faults.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sram_ut2 is
generic(ADD_BUS : integer := 3;
DATA_BUS : integer := 7);
port (CLOCK : in std_logic;
CE : in std_logic;
WE : in std_logic;
RD : in std_logic;
ADDRESS : in std_logic_vector(ADD_BUS downto 0);
DATAIN : in std_logic_vector(DATA_BUS downto 0);
DATAOUT : out std_logic_vector(DATA_BUS downto 0));
end sram_ut2;
architecture Behavioral of sram_ut2 is
type ram_type is array (0 to (2**(ADD_BUS + 1)) - 1) of
std_logic_vector(DATA_BUS downto 0);
signal RAM : ram_type;
signal A : std_logic_vector(DATA_BUS downto 0);
begin
write_read: process (CE, CLOCK, DATAIN, ADDRESS)
begin
if (CE = '1') then
for i in 0 to (2**(ADD_BUS + 1 ) - 1) loop
RAM(i) <= (others => '0');
end loop;
DATAOUT <= (others => 'Z');
elsif (CLOCK'event and CLOCK = '1') then
if (WE = '1') then
--Introducing stuck at 0 fault at bit 0 of location 0
if (ADDRESS = "0000") then
RAM(conv_integer(ADDRESS)) <= (DATAIN and "11111110");
--Introducing stuck at 1 fault at bit 7 of location 1
elsif (ADDRESS = "0001") then
RAM(conv_integer(ADDRESS)) <= (DATAIN or "10000000");
--Introducing 0 to 1 transition fault in bit 5 of location 2
elsif (ADDRESS = "0010") then
if ((RAM(conv_integer(ADDRESS))
and "00100000") = "00000000") then
RAM(conv_integer(ADDRESS)) <= DATAIN and "11011111";
else
RAM(conv_integer(ADDRESS)) <= DATAIN;
end if;
--Introducing 1 to 0 transition fault in bit 2 of location 3
elsif (ADDRESS = "0011") then
if ((RAM(conv_integer(ADDRESS))
and "00000100") = "00000100") then
RAM(conv_integer(ADDRESS)) <= DATAIN or "00000100";
else
RAM(conv_integer(ADDRESS)) <= DATAIN;
end if;
--Introducing inversion coupling fault between cells ofdifferent
--bytes(4 and 5)
--A transition in bit 6 of loc. 4 causes bit 6 of location 5 to
--be inverted
elsif (ADDRESS = "0100") then
if (ADDRESS = "0100") then
RAM(conv_integer(ADDRESS)) <= DATAIN ;
if (RAM(conv_integer(ADDRESS)) = "11111111") then
RAM(5) <= RAM(5) or "01000000";
elsif (RAM(conv_integer(ADDRESS)) = "00000000") then
RAM(5) <= RAM(5) and "10111111";
end if;
else
RAM(conv_integer(ADDRESS)) <= DATAIN;
end if;
-- Introducing ADDRESS decoder faults
-- Fault 1+2: ADDRESS of 8, no location is accessed
elsif (ADDRESS = "1000") then
null;
-- Fault 3+4: ADDRESS of 9 locations 9 and 15
-- are accessed simultaneously
-- Location 15 is also accessed when ADDRESS 15 is applied
elsif (ADDRESS = "1001") then
RAM(conv_integer(ADDRESS)) <= DATAIN;
RAM(conv_integer(15)) <= DATAIN;
--Fault 1+3: ADDRESS of 10, locations 10 and 14
-- are accessed, but location 14 is not accessed when
-- ADDRESS 14 is applied
elsif (ADDRESS = "1010") then
if (ADDRESS = "1010") then
RAM(conv_integer(ADDRESS)) <= DATAIN;
RAM(conv_integer(ADDRESS + 4)) <= DATAIN;
elsif (ADDRESS = "1110") then
null;
end if;
--Fault 2+4: With ADDRESS of 11 or 13, location 13 is accessed,
-- so location 11 is never accessed
elsif (ADDRESS = "1011" or ADDRESS = "1101") then
RAM(13) <= DATAIN;
--Misdirected address fault (decoder fault)
--With ADDRESS 12, location 7 is accessed not location 12
--when ADDRESS 7, no location is access
elsif (ADDRESS = "1100") then
RAM(7) <= DATAIN;
else
RAM(conv_integer(ADDRESS)) <= DATAIN;
end if;
elsif (RD = '1') then
DATAOUT <= RAM(conv_integer(ADDRESS));
end if;
end if;
end process;
end Behavioral;