i wrote a vhdl prog for file reading and it worked without any prob in ModelSim. My next step is doing the same in Xilinx VirtexII Pro board and observing the output.. however, the file reading feature is not working properly..
this is my code segment:
subtype word is std_logic_vector(15 downto 0);
type initz is file of word;
begin
P: process (reset)
file datain : initz open read_mode is "init.txt";
variable L : Line;
begin
if (reset='1') then
while not(endfile(datain)) loop
readline(datain, L); -->shows error here
read(L,val);
end loop;
error:readline should not contain these operands in this context
wat is wrong wit my code?? how do i make it work fr the FPGA board??
this is my code segment:
subtype word is std_logic_vector(15 downto 0);
type initz is file of word;
begin
P: process (reset)
file datain : initz open read_mode is "init.txt";
variable L : Line;
begin
if (reset='1') then
while not(endfile(datain)) loop
readline(datain, L); -->shows error here
read(L,val);
end loop;
error:readline should not contain these operands in this context
wat is wrong wit my code?? how do i make it work fr the FPGA board??