Hi guys
Hi jeppe as well. Im about done with my complete real time vhdl clock. Ive set all the counter perfectly, and also have a set feature to set the time , mins and hours. I only need little bit of help to finish the project. i Hope you can help me on this please.
i) Theres one simple thing but i cant figure it out. the HRTWO output which basically is responsible for the second hour display only goes from 0 to 1 and back 0 accordingly. I mean thats how a real clock works anyway. So i hve the counter set properly, but when im in set mode, i cant seem to make it so i can set its value to either 0 or 1. i dont know because its weird, as its only std logic and the rest (minone, mintwo, hrone) are std logic vectors
ii) I have the code for A and P set which replicate the AM AND PM of a clock. I just need it to switch to either when the counter enters a certain stage.
my code is attached.
thanks!!
Hi jeppe as well. Im about done with my complete real time vhdl clock. Ive set all the counter perfectly, and also have a set feature to set the time , mins and hours. I only need little bit of help to finish the project. i Hope you can help me on this please.
i) Theres one simple thing but i cant figure it out. the HRTWO output which basically is responsible for the second hour display only goes from 0 to 1 and back 0 accordingly. I mean thats how a real clock works anyway. So i hve the counter set properly, but when im in set mode, i cant seem to make it so i can set its value to either 0 or 1. i dont know because its weird, as its only std logic and the rest (minone, mintwo, hrone) are std logic vectors
ii) I have the code for A and P set which replicate the AM AND PM of a clock. I just need it to switch to either when the counter enters a certain stage.
my code is attached.
thanks!!