Four Bit Adder Help For ALU

[Alterah]

Ok, I am very new to VHDL and my understanding is definitely not the best. So far I feel like I understand most of what we've done...however, I don't think it has been taught all that clearly (though that could just be me). Anyhow, I was able to design the code for the four bit adder and the code I have works.

However, I need to use the adder in an ALU. After looking at vectors they appear to make the code easier, but I am having difficulties understanding how to properly use them. I am to use my four bit adder, AND bitwise, OR bitwise, and XOR bitwise in the ALU. I will use a 4-1 MUX to select the correct input to output to a seven segment display. My first problem, though, is getting my adder to function properly with vectors.

Here's the code for my adder (without using vectors):

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY FourBitAdder IS
PORT (
A1,A2,A3,A4 : IN STD_LOGIC;
B1,B2,B3,B4 : IN STD_LOGIC;
S1,S2,S3,S4,C5: OUT STD_LOGIC);
END FourBitAdder;

ARCHITECTURE Structure1 OF FourBitAdder IS
	COMPONENT ONEBITADDER IS
		PORT (
		A,B,C_in : IN STD_LOGIC;
		S_out,C_out : OUT STD_LOGIC);
	END COMPONENT ONEBITADDER ;
	
	SIGNAL C2: STD_LOGIC;
	SIGNAL C3: STD_LOGIC;
	SIGNAL C4: STD_LOGIC;
	
BEGIN
	A1B1: ONEBITADDER 
		PORT MAP(
			A => A1,
			B => B1,
			C_in => '0', [COLOR="Red"]Doesn't have to be zero...I am assuming[/COLOR]
			S_out => S1,
			C_out => C2);
			
	A2B2: ONEBITADDER 
		PORT MAP(
			A => A2,
			B => B2,
			C_in => C2,
			S_out => S2,
			C_out => C3);
			
	A3B3: ONEBITADDER 
		PORT MAP(
			A => A3,
			B => B3,
			C_in => C3 ,
			S_out => S3,
			C_out => C4);
	A4B4: ONEBITADDER 
		PORT MAP(
			A => A4,
			B => B4,
			C_in => C4,
			S_out => S4,
			C_out => C5);
			
END ARCHITECTURE Structure1;

-------------------------
Here's the code for ONEBITADDER

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY ONEBITADDER IS
PORT (
A,B,C_in : IN STD_LOGIC;
S_out,C_out : OUT STD_LOGIC);
END ONEBITADDER ;

ARCHITECTURE Behavior of ONEBITADDER IS
BEGIN
S_out <= (A XOR B) XOR C_in;
C_out <= (A AND B) OR ((A XOR B) AND C_in);
END ARCHITECTURE Behavior;

Ok, so that's what works. Here's my attempt to convert it to vectors:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY FourBitAdd IS
PORT (
	A_in  		: IN  STD_LOGIC_VECTOR(3 downto 0);
	B_in  		: IN  STD_LOGIC_VECTOR(3 downto 0);		
	S			: OUT STD_LOGIC_VECTOR(4 downto 0)
	 );
END FourBitAdd;

ARCHITECTURE Structure1 OF FourBitAdd IS
	COMPONENT ONEBITADD IS
	PORT (
		A  		: IN  STD_LOGIC_VECTOR(3 downto 0);
		B  		: IN  STD_LOGIC_VECTOR(3 downto 0);
		C_in	: IN  STD_LOGIC_VECTOR(3 downto 0);
		S_out	: OUT STD_LOGIC_VECTOR(4 downto 0);
		C_out	: OUT STD_LOGIC_VECTOR(3 downto 0)
	 );
	END COMPONENT ONEBITADD;
	SIGNAL C: STD_LOGIC_VECTOR (3 downto 0);

BEGIN
	AB: ONEBITADD

		PORT MAP(
			A => A_in(3 downto 0),
			B => B_in(3 downto 0),
			C_in(0) => '0',
			S_out => S(4 downto 0),
			C_out => C(3 downto 0)
			);
	
		
END ARCHITECTURE Structure1;

--------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY ONEBITADD IS
PORT (
A  		: IN  STD_LOGIC_VECTOR(3 downto 0);
B  		: IN  STD_LOGIC_VECTOR(3 downto 0);
C_in	: IN  STD_LOGIC_VECTOR(3 downto 0);
S_out	: OUT STD_LOGIC_VECTOR(4 downto 0);
C_out	: OUT STD_LOGIC_VECTOR(3 downto 0)
	 );
END ONEBITADD;

ARCHITECTURE Behavior of ONEBITADD IS
BEGIN
S_out(4 downto 0) <= (A XOR B) XOR C_in;
C_out(3 downto 0) <= (A AND B) OR ((A XOR B) AND C_in);
END ARCHITECTURE Behavior;

Thanks for any help. I am wanting to understand how to properly use vectors. Right now...I feel like I just through the above together...without understanding what I am doing. Also, I am getting an error regarding the sum bit. It was made explicit in class that I would need 5 bits for the output. I am getting an error regarding that. Again..huge thanks for any help or advice...or links to good resources.

 

[joris]

This should work (except for typos maybe, I didn't test it)

I use the original ONEBITADDER entity (it's for one bit so that one stays the same)
The last instantiation is kinda special as the carry-out is stored into S(4) instead of in a carry bit; The rest is a simple modification of the original code;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY FourBitAdd IS
PORT (
	A_in  		: IN  STD_LOGIC_VECTOR(3 downto 0);
	B_in  		: IN  STD_LOGIC_VECTOR(3 downto 0);		
	S			: OUT STD_LOGIC_VECTOR(4 downto 0)
	 );
END FourBitAdd;

ARCHITECTURE Structure1 OF FourBitAdder IS
	COMPONENT ONEBITADDER IS
		PORT (
		A,B,C_in : IN STD_LOGIC;
		S_out,C_out : OUT STD_LOGIC);
	END COMPONENT ONEBITADDER ;
	
SIGNAL C: STD_LOGIC_VECTOR (3 downto 1);
	
BEGIN
	A1B1: ONEBITADDER 
		PORT MAP(
			A => A(0),
			B => B(0),
			C_in => '0' --yes has to be zero otherwise you calculate A+B+1
			S_out => S(0),
			C_out => C(1));
			
	A2B2: ONEBITADDER 
		PORT MAP(
			A => A(1),
			B => B(1),
			C_in => C(1),
			S_out => S(1),
			C_out => C(2));
			
	A3B3: ONEBITADDER 
		PORT MAP(
			A => A(2),
			B => B(2),
			C_in => C(2) ,
			S_out => S(2),
			C_out => C(3));
	A4B4: ONEBITADDER 
		PORT MAP(
			A => A(3),
			B => B(3),
			C_in => C(3),
			S_out => S(3),
			C_out => S(4));
			
END ARCHITECTURE Structure1;

 

[Alterah]

So, it looks like you still have to specify, for the adder at least, which vector element each term goes into. I think that was my problem...I thought that I had to show it as:

BEGIN
	AB: ONEBITADD

		PORT MAP(
			A => A_in(3 downto 0),
			B => B_in(3 downto 0),
			C_in(0) => '0',
			S_out => S(4 downto 0),
			C_out => C(3 downto 0)
			);
	
		
END ARCHITECTURE Structure1;

In the architecture. But..since it looks like I need to just specify each vector element separately...I should get something that looks very similar to to my original code (without vectors). Does that sound correct? I also need to have the output have 8 bits, but I wanted to try and tackle this one step at a time. For the 8 bit issue I'd just declare the sum vector like so:

PORT (
	A_in  		: IN  STD_LOGIC_VECTOR(3 downto 0);
	B_in  		: IN  STD_LOGIC_VECTOR(3 downto 0);		
	S			: OUT STD_LOGIC_VECTOR(7 downto 0)
	 );
END FourBitAdd;
.
.
.
S(7)  => '0';
S(6)  => '0';
S(5)  => '0';

The assignments would just come right before the END ARCHITECTURE.
Thank you for your assistance. It was driving me nuts...because I know I still have a lot left.

 

[joris]

In the architecture. But..since it looks like I need to just specify each vector element separately...I should get something that looks very similar to to my original code (without vectors). Does that sound correct?

Yeah that's right - it is really only a syntax difference.

 

[Alterah]

Thanks for the help. Hopefully now I can figure out the rest of the assignment.