C
cvc.training
Advanced Verification with Aldec’s Riviera-Pro
Given the ever growing complexities of SoC designs, the task of
verifying these SoCs is herculean indeed! A series of innovative, path
breaking technologies have emerged over the last decade to address the
verification challenges. Industry is seeing a culmination of these
techniques in the form of new languages such as IEEE 1850-PSL, IEEE
1666 SystemC etc. Every language provides a complementary strength,
and addresses specific problem. Recently, many of these separate
language capabilities have been integrated into single language and
are available as IEEE-1800 standard SystemVerilog (SV). SV is poised
to be the choice of DV engineers for many years to come due to the
overwhelming support from all tools and the greater eco-system of
trainings, books and papers.
Aldec has been the primary EDA provider for various ASIC and FPGA
design tasks for over 24 years now. Riviera-PRO is a proven high-
performance, mixed-language simulation engine with advanced debugging
tools for ASIC and FPGA design teams. Riviera-PRO supports VHDL,
Verilog®, SystemVerilog, SystemC, C/C++, PSL and OVA assertions from
one common design environment. Riviera-PRO enables mixed RTL
debugging, long regression testing, timing simulation and electronic
system level (ESL) verification.
IEEE 1800, SystemVerilog is a major extension to Verilog-2001, adding
significant new features to Verilog for verification, design and
synthesis. Enhancements range from simple enhancements to existing
constructs, addition of new language constructs to the inclusion of a
complete Object-Oriented paradigm features. We at CVC have been on the
top of leading edge verification technologies for the past half-a-
decade. We recently setup an advanced verification environment for a
memory controller using SystemVerilog and Aldec’s Riviera-PRO. In this
seminar an share that anecdote with the attendees. We walk through the
following topics:
Advanced Verification techniques
Verification Architecture for Memory controller
Key SystemVerilog features used in this verification with code
snippets
Screenshots of important Riviera-PRO features that helped us in the
process
To attend this seminar, confirm your registration by sending an email
to (e-mail address removed) with subject as CVC_Verif_Aldec Seminar.
Please include the following details in your email.
Name:
Company Name:
Official Email ID:
Contact Number:
Venue: CVC Office (Ground Floor)
Date: 23rd July 2008 at 11.00 A.M
Agenda: 1 hour presentation on Advanced Verification Using Aldec
followed by demo
Given the ever growing complexities of SoC designs, the task of
verifying these SoCs is herculean indeed! A series of innovative, path
breaking technologies have emerged over the last decade to address the
verification challenges. Industry is seeing a culmination of these
techniques in the form of new languages such as IEEE 1850-PSL, IEEE
1666 SystemC etc. Every language provides a complementary strength,
and addresses specific problem. Recently, many of these separate
language capabilities have been integrated into single language and
are available as IEEE-1800 standard SystemVerilog (SV). SV is poised
to be the choice of DV engineers for many years to come due to the
overwhelming support from all tools and the greater eco-system of
trainings, books and papers.
Aldec has been the primary EDA provider for various ASIC and FPGA
design tasks for over 24 years now. Riviera-PRO is a proven high-
performance, mixed-language simulation engine with advanced debugging
tools for ASIC and FPGA design teams. Riviera-PRO supports VHDL,
Verilog®, SystemVerilog, SystemC, C/C++, PSL and OVA assertions from
one common design environment. Riviera-PRO enables mixed RTL
debugging, long regression testing, timing simulation and electronic
system level (ESL) verification.
IEEE 1800, SystemVerilog is a major extension to Verilog-2001, adding
significant new features to Verilog for verification, design and
synthesis. Enhancements range from simple enhancements to existing
constructs, addition of new language constructs to the inclusion of a
complete Object-Oriented paradigm features. We at CVC have been on the
top of leading edge verification technologies for the past half-a-
decade. We recently setup an advanced verification environment for a
memory controller using SystemVerilog and Aldec’s Riviera-PRO. In this
seminar an share that anecdote with the attendees. We walk through the
following topics:
Advanced Verification techniques
Verification Architecture for Memory controller
Key SystemVerilog features used in this verification with code
snippets
Screenshots of important Riviera-PRO features that helped us in the
process
To attend this seminar, confirm your registration by sending an email
to (e-mail address removed) with subject as CVC_Verif_Aldec Seminar.
Please include the following details in your email.
Name:
Company Name:
Official Email ID:
Contact Number:
Venue: CVC Office (Ground Floor)
Date: 23rd July 2008 at 11.00 A.M
Agenda: 1 hour presentation on Advanced Verification Using Aldec
followed by demo