FSM simulation

[Tomas]

Hi,

I'm having big problems simulating a very simple fsm in modelsim (I
write code in xilinx ISE). Problems arise as soon as try to simulate in
something different than behavioral model
(post-translate,post-map,post-place).

this is the FSM:

type STATE_TYPE is
(FS_IDLE,FS_RECV_INST,FS_RECV_ADDR,FS_SEND_DATA,FS_WRITE_DATA);
signal STATE, NEXTSTATE : STATE_TYPE;
signal STATECLK: bit;

begin
REG:
process (SCK,CS_N)
begin
if CS_N='1' then
-- reset
STATE<=FS_IDLE;
elsif (SCK'event and SCK='1') then
STATE<=NEXTSTATE;
STATECLK<=not STATECLK;
end if;
end process REG;

FSM_P:
process(STATECLK)
variable curr_indx:integer range 0 to 32;
begin
NEXTSTATE<=STATE;
case STATE is
when FS_IDLE => curr_indx:=0;
NEXTSTATE<=FS_RECV_INST;
TEST<="11111111";
when FS_RECV_INST => if curr_indx=4 then
NEXTSTATE<=FS_RECV_ADDR;
else
curr_indx:=curr_indx+1;
end if;

TEST<=conv_std_logic_vector(curr_indx,8);
when FS_SEND_DATA => TEST<="11000000";
when FS_WRITE_DATA => TEST<="10000000";
when others => TEST<="01000000";
end case;
end process FSM_P;
end Behavioral;

TEST is just a std_logic_vector(7 downto 0) I use for debug purposes.

If simulating behavioral model everything works as expected, curr_indx
increases until 4 then state is changed to FS_RECV_ADDR.

But when simulating post-translate model curr_indx is immediatly = 4,
instead of increasing at each change of of STATECLK. It is as if FSM_P
would be looped very fast instead of triggering to STATECLK changes.

Thanks in advance for help,
Tomas

 

[Benjamin Todd]

Hey Tomas,

I'm a bit confused by the code you posted... A couple of things..

Firstly, the sensitivity list of your FSM process only contains STATE_CLK,
that's a bit of a cheat... And i'm surprised it doesn't warn you about that
when you compile the file.
Secondly, State_CLK is never given a reset value... And then FS_RCV_ADD
state doesn't exist, my guess is that it's sending you to the Others state,
although i'm sure if that's what you intend?
Then of course, you've the isuue of your FSM hanging as it reaches the last
two of your states... It's never reassigned...

Have a fiddle, then repost some code!
Ben

 

[Tomas]

Hi,

first of all thanks for taking time answering my question.

I'm trying to implement a very simple eeprom with an spi bus. As you
probably know this is a very simple serial bus that first receives the
instruction (read/write/erase) then eventually the address (read/write
case) and then finally the data.

So I though to make 5 states
idle,receive_instruction,receive_address,receive_data,send_data.
Suppose instruction,address and data are 8 bit long, In each state I'll
have to stay 8 clock (SCK) periods, then finally change state.

For example:
signal TMP_RECV_INSTRUCTION: std_logic_vector(7 downto 0);
.....
.....

when FS_RECV_INST =>
TMP_RECV_INSTRUCTION(curr_indx)<=SI -- SI=serial
input
if curr_indx=8 then
NEXTSTATE<=FS_RECV_ADDR; --
instruction received,get address
curr_indx:=0;
else
curr_indx:=curr_indx+1;
-- still data to get
end if;


so I need to enter the FSM_P process only when STATE_CLK changes,
that's why I though it was a good idea to have the STATE_CLK signal.
Why is thi a bit of a cheat? By the way I receive no warns about that.

Sorry for the bad code posted, but it I was *debugging* just the
behaviour of the FS_RECV_INST state. I just can't understand why it
works (curr_indx increases after each SCK period) simulating the
behavioral model and not with the other models.

Thanks again,
Tomas