General question on access SRAM

[picnanard]

I want control the read and write (SRAM single data port) with FPGA I want stick a read cycle after write cycle. See below
CS ----\_________________/------
RD ----\_______/-----------------
WR -------------\________/-----------

According your experience
Can I do that?
The data sheet indicate the data still on the bus 8ns after the RD raising edge.