generate and std_logic_vector array issue

[vince00001]

Hello,

I use Quartus II version 7.0 Webedition. In order to implement video application I need to generate 70 lpm_dff register and link the first register output with the second register input and the second output with the third input etc....
The first register is linked with right signal (STD_LOGIC_VECTOR (7 downto 0)) and every wire beetwen the different register are std_logic_vector (7 downto 0) in an array (zR_array).
But error report say zR_array does not agree with the usage as std_logic_vector.


-----------------BLOCK SIGNALS------------------------------------------

ENTITY WinBLK IS
PORT
(
Right : IN STD_LOGIC_VECTOR (7 downto 0);
Left : IN STD_LOGIC_VECTOR (7 downto 0);
clk : IN STD_LOGIC;
);
END WinBLK;

ARCHITECTURE WinProcess OF WinBLK IS

-----------------------------------CONSTANT-----------------------------------------------

constant Maxfor : integer := 69;

--------INTERNAL SIGNALS AND ARRAY-----------------------------------

TYPE zR_array IS ARRAY (natural range <>) OF std_logic_vector (7 downto 0);

-------------------------------COMPONENT BLOCKS-------------------------------------------

-----------REGISTER 8 Bits for Right sample (70)
component lpm_dff8

PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
enable : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END component lpm_dff8;

BEGIN

--------------------------------MAIN PROCESS--------------------------------------------

g1:for i in 0 to (Maxfor +1) GENERATE

g2:if i = 0 generate
dffx: lpm_dff8 port map ( clk, Right, EnableRight, zR_array );--regRN
end generate g2;

g3:if (i > 0) and i < (Maxfor) generate
-- dffx: lpm_dff8 port map ( clk, zR_array(i), EnableRight, zR_array(i+1) );--regRN
end generate g3;

g4:if i <= (Maxfor + 1) generate
-- dffx: lpm_dff8 port map ( clk, zR_array(i), EnableRight, Right_INT );--regRN
end generate g4;

END GENERATE g1;

h1:for i in 0 to (Maxfor+1) GENERATE

h2:if (i > 0) and i < (Maxfor+1) generate
-- dffy: lpm_dff8 port map ( clk, Left_INT, EnableRight, zL_array(i+1) );--regRN
end generate h2;

END GENERATE h1;

END WinProcess;

ERROR REPORT:

Error (10476): VHDL error at winBLK.vhd(97): type of identifier "zR_array" does not agree with its usage as std_logic_vector type
Error (10558 ): VHDL error at winBLK.vhd(97): cannot associate formal port "q" of mode "out" with an expression

Can someone help???

Thanks in advance.
Regards,
Vince

 

[quantum_dot]

It appears that you are passing a type array to signal q which is a std_logic_vector. This is the possible cause of the problem.

TYPE zR_array IS ARRAY (natural range <>) OF std_logic_vector (7 downto 0);

q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)

Try to pass the array index to the component instantiation.

:driver:

 

[vince00001]

reply

Hello quantum_dot,

I passed the array index to the component like this:

--------------------------------------------------------------------------
-----------REGISTER 8 Bits for Right sample (70)
component lpm_dff8

PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
enable : IN STD_LOGIC ;
q : OUT zR_array (0 to 69)
);
END component lpm_dff8;
--------------------------------------------------------------------------

for the generate part of the program I have:

--------------------------------MAIN PROCESS--------------------------------------------

g1:for i in 0 to (Maxfor +1) GENERATE

g2:if i = 0 generate
lpm_dffx: lpm_dff8 port map ( clk, Right, EnableRight, zR_array(i) );--regRN (the matter is with this line)
end generate g2;

g3:if (i > 0) and i < (Maxfor) generate
-- lpm_dffx: lpm_dff8 port map ( clk, zR_array(i), EnableRight, zR_array(i+1) );--regRN
end generate g3;

g4:if i <= (Maxfor + 1) generate
-- lpm_dffx: lpm_dff8 port map ( clk, zR_array(i), EnableRight, Right_INT );--regRN
end generate g4;

END GENERATE g1;

h1:for i in 0 to (Maxfor+1) GENERATE

h2:if (i > 0) and i < (Maxfor+1) generate
-- lpm_dffy: lpm_dff8 port map ( clk, Left_INT, EnableRight, zL_array(i+1) );--regRN
end generate h2;

END GENERATE h1;

END WinProcess;

--------------------------------------------------------------------------

ERROR REPORT:
Error (10305): VHDL Type Conversion error at winBLK.vhd(93): integer type cannot be converted to zR_array type
Error (10558 ): VHDL error at winBLK.vhd(93): cannot associate formal port "q" of mode "out" with an expression

I think right signal (IN std_logic_vector 7 downto 0) put on the input of the lpm_dff8 component doesn't agree with the output array (zR_array).

Thanks in advance.
Best regards,
Vince

 

[quantum_dot]

In my understanding you should not define signal "q" as array in your component.
q : OUT zR_array (0 to 69) -- this is wrong

the way you defined in your last construct was okay

q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)

And then pass the array index as you have done in your current construct. This should work.

If this also does not work, then a solution can be - define a dummy signal 'q_temp' to generate the value of std_logic_vector and then assign the same to the required array index.

signal q_temp : std_logic_vector( 7 downto 0 );

g2:if i = 0 generate
lpm_dffx: lpm_dff8 port map ( clk, Right, EnableRight, q_temp );
end generate g2;

zR_array(i) <= q_temp ;


Hope this time the problem is solved

:dirver: