generating within a case statement

[colin]

Hi

I have written some code that I hate and would like some help

I have an array of registers which I have generated of static size
(comes into the entity via a generic. I now need to read the registers
as follows:-

READ_REGS: process (reset,clk)
begin
if (reset='1') then
reg <= (others => '0');
elsif (clk'event and clk='1') then

if ( read_oe = '1' ) then

case (addr(4 downto 2)) is
when ("000") =>
read_data <= register(0);
when ("001") =>
read_data <= register(1);
when ("010") =>
read_data <= register(2);
when ("011") =>
read_data <= register(3);

when others => read_data <= (others => 'X'); end case;

end if;

Obviously I want the case statement to be able to read an unknown
number of registers. Converting addr(4 downto 0) to an integer is easy
but then I'm stuck as to how to put a generate into a case statement.

Any help appreciated

Colin

 

[Egbert Molenkamp]

Hi

I have written some code that I hate and would like some help

I have an array of registers which I have generated of static size
(comes into the entity via a generic. I now need to read the registers
as follows:-

READ_REGS: process (reset,clk)
begin
if (reset='1') then
reg <= (others => '0');
elsif (clk'event and clk='1') then

if ( read_oe = '1' ) then

case (addr(4 downto 2)) is
when ("000") =>
read_data <= register(0);
when ("001") =>
read_data <= register(1);
when ("010") =>
read_data <= register(2);
when ("011") =>
read_data <= register(3);

when others => read_data <= (others => 'X'); end case;

end if;

Obviously I want the case statement to be able to read an unknown
number of registers. Converting addr(4 downto 0) to an integer is easy
but then I'm stuck as to how to put a generate into a case statement.

Any help appreciated

Colin

I have the feeling the case statement is not needed at all.
Probably the following replaces the case:
read_data <= register(to_integer(unsigned(addr(4 downto 2))));

Egbert Molenkamp

 

[Ralf Hildebrandt]

colin wrote:

Obviously I want the case statement to be able to read an unknown
number of registers.

constant reg_number : integer := 8;
constant reg_size : integer := 16;
signal register_1D_array : std_ulogic_vector(number*reg_size-1 downto 0);

-> 8 registers with 16 bit datawidth each.
Reading the registers is easy (reg_addr selects which one):

data_out <= register_1D_array((reg_addr+1)*reg_size-1 downto reg_addr*reg_size);

If your synthesis tool gets stuck with this description of a mux, take a for-loop:

for N in 0 to reg_size-1 loop
data_out(N) <= register_1D_array(reg_addr*reg_size+N);
end loop;


A similar solution is possible with a 2D array, which may be more human-readable, but may
make trouble with some older synthesis tools (or if you ever want to convert your code to
Verilog ;-)).

Ralf

 

[colin_toogood]

Thanks for both ideas, I will try them out next week.

Thanks

colin