generating

Z

zlotawy

Hello,

I have Input Port named Port.

Size of Port is generated by generic.

For example I have:

Port(0,0000)
Port(0,0001)
Port(0,0101)
Port(0,1111)

and

Port(1,0000)
Port(1,0101)
Port(1,1110)
Port(1,1001)

and

Port(2,0101)
Port(2,1010)
Port(2,1111)
Port(2,0000)

I would like to join all vectors where Port = Port(0,X) or Port = Port(1,X).

QAZ(size_generated-1..0) <= Port(0,X)&Port(1,X).

and size_generated = number_of_vectors * number_of_bits_in_vector.

But I do not know how many vectos wll be generated.... 3, 6 maye 1000. I can
not write "Port(0,X)&Port(1,X)." It must be like "Port(Y,X)" and Y should be
calculated.


I think I should use "generate".

for i IN 0 to number_of_vectors-1 generate
??????????
end generate;

But i do not know by what code should I replace "??"

Maybe someone can help me?


Regards,
zlotawy
 
J

Jonathan Bromley

Hello,

I have Input Port named Port.

Size of Port is generated by generic.

For example I have:

Port(0,0000)
Port(0,0001)
Port(0,0101)
Port(0,1111)

and

Port(1,0000)
Port(1,0101)
Port(1,1110)
Port(1,1001)

and

Port(2,0101)
Port(2,1010)
Port(2,1111)
Port(2,0000)

I would like to join all vectors where Port = Port(0,X) or Port = Port(1,X).

QAZ(size_generated-1..0) <= Port(0,X)&Port(1,X).

and size_generated = number_of_vectors * number_of_bits_in_vector.

But I do not know how many vectos wll be generated.... 3, 6 maye 1000. I can
not write "Port(0,X)&Port(1,X)." It must be like "Port(Y,X)" and Y should be
calculated.


I think I should use "generate".

for i IN 0 to number_of_vectors-1 generate
??????????
end generate;

But i do not know by what code should I replace "??"

I don't think you need "generate". How about
something like this:

constant big_bus_width: integer :=
number_of_vectors * bits_per_vector;
signal big_bus: std_logic_vector(0 to big_bus_width-1);

...
process (Port)
begin
for i in 0 to number_of_vectors-1 loop
big_bus
(
i*bits_per_vector to
i*bits_per_vector + bits_per_vector - 1
)
<= Port(i, X);
end loop;
end process;
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 

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