Generic entities in package

[Olaf Petzold]

Hi,

is it possible to use generic entities inside packages? The following
code will not pass modelsim. The error is:

# ** Error: ../source/vhdl/tb_pkg.vhd(67): near "architecture":
expecting: END

What is wrong?

Thanks
Olaf

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


package tb_pkg is

component clock_source is
generic (
PERIOD : time := 10 ns;
RESET_TIME : time := 50 ns;
RESET_ACTIVE : std_logic := '1');
port (
clk : out std_logic;
reset : out std_logic;
stop : in std_logic);
end component;

end package;


package body tb_pkg is

-- entity clock_source is
-- generic (
-- PERIOD : time := 10 ns;
-- RESET_TIME : time := 30 ns;
-- RESET_ACTIVE : std_logic := '1');
-- port (
-- clk : out std_logic;
-- reset : out std_logic;
-- stop : in std_logic);
-- end entity;

architecture behavioral of clock_source is -- line 67
begin
process (clk, reset, stop) is
begin
clk <= '0';

if (now < RESET_TIME) then
reset <= RESET_ACTIVE;
else
reset <= not RESET_ACTIVE;
end if;

if stop then wait; end if;

wait for PERIOD/2;
clk <= '1';
wait for PERIOD/2;

end process;
end architecture;

end package;

 

[Mike Treseler]

is it possible to use generic entities inside packages?

I can *instance* entities
but I can only package declarations.

-- Mike Treseler