graphic representation of a vhdl project

[marc]

Hi
I have finished a VHDL project : an graphic adaptater with a FPGA.
Now, I write the documentation and I search a tools able to build a
graphic representation of architectures of entities of my project.
I have try Doxygen, but Doxygen build only class diagram.
To sum up, I search a tool as the function of FPGA advantage (lattice)
which build a graphic representation of my design.
..marc

 

[Mike Treseler]

To sum up, I search a tool as the function of FPGA advantage (lattice)
which build a graphic representation of my design.

Most synthesis tools include an rtl viewer
I use this feature to browse a design and print
interesting levels to a pdf.

-- Mike Treseler

 

[marc]

Most synthesis tools include an rtl viewer
I use this feature to browse a design and print
interesting levels to a pdf.

-- Mike Treseler

ok, good news and can you give me an example ?, actualy i use quartus
2 and modelsim.

 

[Mike Treseler]

ok, good news and can you give me an example ?, actualy i use quartus
2 and modelsim.

See the 'object' links here:
http://mysite.verizon.net/miketreseler/
You will need the licensed version of quartus.

-- Mike Treseler

 

[marc]

Excellent, thank you.
I use the web edition of quartus. I will test with an other version
because i have not found this options.