Forums
New posts
Search forums
Members
Current visitors
Log in
Register
What's new
Search
Search
Search titles only
By:
New posts
Search forums
Menu
Log in
Register
Install the app
Install
Forums
Archive
Archive
VHDL
Hardware book like "Code Complete"?
JavaScript is disabled. For a better experience, please enable JavaScript in your browser before proceeding.
Reply to thread
Message
[QUOTE="Andy, post: 1893511"] Using variables for the register itself also means that the register can be read back internally, which you can't do with the output port signal. Variable assignment/update overhead during simulation is less than that of signals. Using variables for the registers, then a final output signal assignment from the variable (within the process) removes the need for a separate combo process or concurrent assignment, and the simulation overhead involved with that too. Andy [/QUOTE]
Verification
Post reply
Forums
Archive
Archive
VHDL
Hardware book like "Code Complete"?
Top