A
a_Conan
Hi,
I am using the HDL Author,
my problem that i have designed this code in HDL Author:
-----------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
ENTITY test3 IS
PORT(
In0 : IN unsigned (15 DOWNTO 0);
clock: IN std_logic;
Out0 : OUT unsigned (15 DOWNTO 0)
);
END test3 ;
ARCHITECTURE struct OF test3 IS
BEGIN
exdd: process(clock)
begin
Out0 <= In0 sll 2;
end process exdd;
END struct;
---------------------------
it gives this error message!!!!!!!!!!!!1
ERROR: D:/Sara/Tests/hdl/test3_struct.vhd(57): near "sll": expecting:
';'
Why Why !!!!
I am using the HDL Author,
my problem that i have designed this code in HDL Author:
-----------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
ENTITY test3 IS
PORT(
In0 : IN unsigned (15 DOWNTO 0);
clock: IN std_logic;
Out0 : OUT unsigned (15 DOWNTO 0)
);
END test3 ;
ARCHITECTURE struct OF test3 IS
BEGIN
exdd: process(clock)
begin
Out0 <= In0 sll 2;
end process exdd;
END struct;
---------------------------
it gives this error message!!!!!!!!!!!!1
ERROR: D:/Sara/Tests/hdl/test3_struct.vhd(57): near "sll": expecting:
';'
Why Why !!!!