Hi pple
this is a part of my coding
and i got a serious error while trying to synthesize it
the line which was highlighted in red
ERROR stated
ERROR:Xst:779 - "D:/PS2_control/PS2_control/PS2_Ctrl.vhd" line 77: 'Others' is in unconstrained array aggregate.
process (Clk,Reset)
begin
if Reset='1' then
PS2_Datr <= '0';
PS2_Clk_f <= '0';
Filter <= (others=>'0');
Fall_Clk <= '0';
elsif rising_edge (Clk) then
PS2_Datr <= PS2_Data and PS2_Data; -- also turns 'H' into '1'
Fall_Clk <= '0';
Filter <= (PS2_Clk and PS2_CLK) & Filter(Filter'high downto 1);
if Filter = Filter_t'(others=>'1') then
PS2_Clk_f <= '1';
elsif Filter = Filter_t'(others=>'0') then
PS2_Clk_f <= '0';
if PS2_Clk_f = '1' then
Fall_Clk <= '1';
end if;
end if;
end if;
end process;
up till now i still cannot find any solutions to it. probably cause im a beginner in FPGA too..
this is a part of my coding
and i got a serious error while trying to synthesize it
the line which was highlighted in red
ERROR stated
ERROR:Xst:779 - "D:/PS2_control/PS2_control/PS2_Ctrl.vhd" line 77: 'Others' is in unconstrained array aggregate.
process (Clk,Reset)
begin
if Reset='1' then
PS2_Datr <= '0';
PS2_Clk_f <= '0';
Filter <= (others=>'0');
Fall_Clk <= '0';
elsif rising_edge (Clk) then
PS2_Datr <= PS2_Data and PS2_Data; -- also turns 'H' into '1'
Fall_Clk <= '0';
Filter <= (PS2_Clk and PS2_CLK) & Filter(Filter'high downto 1);
if Filter = Filter_t'(others=>'1') then
PS2_Clk_f <= '1';
elsif Filter = Filter_t'(others=>'0') then
PS2_Clk_f <= '0';
if PS2_Clk_f = '1' then
Fall_Clk <= '1';
end if;
end if;
end if;
end process;
up till now i still cannot find any solutions to it. probably cause im a beginner in FPGA too..