Help needed in Control Unit VHDL

[DanielGoh]

Hello, currently I am VHDL code for Control Unit (CU) for GCD Calculator. Here is my code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity CU is
port(clk, reset, start, Eq, Lt : in std_logic;
y : buffer std_logic;
CtrlVec : out std_logic_vector (6 downto 0);
done : out std_logic);
end CU;

architecture CU_arch of CU is
type state is (S0,S1);
signal PS, NS : std_logic;

begin
y <= PS; --- ERROR!!!
STATE_REG:
process(clk, reset) begin
if (reset = '1') then PS <= S0;
elsif (clk'event and clk = '0') then PS <= NS;
end if;
end process STATE_REG;

NS_LOGIC:
process (PS, start, Eq) begin
case PS is
when S0 => if start = '1' then NS <= S1; else NS <= S0; end if;
when S1 => if Eq = '1' then NS <= S0; else NS <= S1; end if;
end case;
end process NS_LOGIC;

OUTPUT_LOGIC:
process (PS, start, Eq, Lt) begin
CtrlVec <= (others => '0'); done <= 0;
case PS is
when S0 => if start = '1' then CtrlVec <= "0111100"; end if;
when S1 => if Eq = '1' then done <= '1'; CtrlVec <= "1000000";
elsif Lt = '1' then CtrlVec <= "0000100";
else CtrlVec <= "0010011";
end if;
end case;
end process OUTPUT_LOGIC;
end CU_arch;


My problem is: How to make the PS as output? I have to display the output y and y should be PS. Thanks!

 

[joris]

I'm seeing these errors:

- You're assigning values of type 'state' to 'PS' and 'NS', but you declared them as std_logic
- You're assiging 0 to done -- probably a typo, it should be '0' (note the quotes)

To fix the problem of assigning PS to y, you can use these ideas:

- Using an constant array describing the mapping

-- in declaration area
type state_mapping is array(state) of std_logic;
constant mapping : state_mapping := (S0 => '0', S1 => '1');

-- in implementation area
y <= mapping(PS);

Or, when you find you need more complicated mappings, use a function,

-- in declaration area
function mapping(s : state) return std_logic is
begin
  case s is
    when S0 => return '0';
    when S1 => return '1';
  end case;
end;

-- in implementation area
y <= mapping(PS);

 

[soonph87]

hi, error still exists saying that PS does not agree with its usage as "state" type.

 

[joris]

You have to declare PS as having type 'state' instead of 'std_logic'