I need some help regarding a VHDL-program i wrote. Its supposed to get a clk of 1MHz and output a clk of 10kHz and a clk of 1kHz:
-------- takterzeugung.vhd -------
library ieee;
use ieee.std_logic_1164.all;
use ieee.Numeric_STD.all;
entity takterzeugung is
port (
gtakt: in std_logic;
takt: out std_logic;
ftakt: out std_logic;
reset: in std_logic
);
end takterzeugung;
architecture behavioral of takterzeugung is
signal c50: std_logic_vector(5 downto 0);
signal c5: std_logic_vector(2 downto 0);
signal tak: std_logic;
signal ftak: std_logic;
begin
process(gtakt, reset)
begin
if (reset = '1') then
c50 <= "000000";
c5 <= "000";
tak <= '0';
ftak <= '0';
elsif (rising_edge(gtakt)) then
if (c50 = "110001") then
c50 <= "000000";
ftak <= not ftak;
else
c50 <= std_logic_vector( unsigned(c50) + 1 );
end if;
end if;
end process;
process(ftak)
begin
if (rising_edge(ftak)) then
if (c5 = "100") then
c5 <= "000";
tak <= not tak;
else
c5 <= std_logic_vector( unsigned(c5) + 1 );
end if;
end if;
end process;
ftakt <= ftak;
takt <= tak;
end behavioral;
--------- takterzeugung.vhd ---------
after this i made a small testbench file to test it with gtkwave:
--------- takterzeugung_tb.vhd ----------
library ieee;
use ieee.std_logic_1164.all;
entity takterzeugung_tb is
end entity;
architecture TB of takterzeugung_tb is
component takterzeugung
port (
gtakt: in std_logic;
takt: out std_logic;
ftakt: out std_logic;
reset: in std_logic
);
end component;
signal gtakt: std_logic;
signal takt: std_logic;
signal ftakt: std_logic;
signal reset: std_logic;
begin
ter: takterzeugung port map (gtakt, takt, ftakt, reset);
process
begin
gtakt <= '0';
wait for 500 ns;
gtakt <= '1';
wait for 500 ns;
end process;
end;
---------- takterzeugung_tb.vhd ---------
ok so now if i run cmd i do the following:
ghdl -a takterzeugung.vhd
ghdl -a takterzeugung_tb.vhd
ghdl -e takterzeugung_tb
till here no errors or anything. Now i want to run the testbench and output the signals into a vcd file:
ghdl -r takterzeugung_tb --stop-time=1000ms --vcd=takterzeugung_tb.vcd
the computer starts working and doesnt stop till ghdl advises to shut down the programm cause smthing went wrong.
The vcd-file is nearly empty and i cant view it with gtkwave.
So my heres my question:
What am i doing wrong? Is my vhdl code wrong? Do i need to add another command in cmd?
Thanks for your help in advance!
-------- takterzeugung.vhd -------
library ieee;
use ieee.std_logic_1164.all;
use ieee.Numeric_STD.all;
entity takterzeugung is
port (
gtakt: in std_logic;
takt: out std_logic;
ftakt: out std_logic;
reset: in std_logic
);
end takterzeugung;
architecture behavioral of takterzeugung is
signal c50: std_logic_vector(5 downto 0);
signal c5: std_logic_vector(2 downto 0);
signal tak: std_logic;
signal ftak: std_logic;
begin
process(gtakt, reset)
begin
if (reset = '1') then
c50 <= "000000";
c5 <= "000";
tak <= '0';
ftak <= '0';
elsif (rising_edge(gtakt)) then
if (c50 = "110001") then
c50 <= "000000";
ftak <= not ftak;
else
c50 <= std_logic_vector( unsigned(c50) + 1 );
end if;
end if;
end process;
process(ftak)
begin
if (rising_edge(ftak)) then
if (c5 = "100") then
c5 <= "000";
tak <= not tak;
else
c5 <= std_logic_vector( unsigned(c5) + 1 );
end if;
end if;
end process;
ftakt <= ftak;
takt <= tak;
end behavioral;
--------- takterzeugung.vhd ---------
after this i made a small testbench file to test it with gtkwave:
--------- takterzeugung_tb.vhd ----------
library ieee;
use ieee.std_logic_1164.all;
entity takterzeugung_tb is
end entity;
architecture TB of takterzeugung_tb is
component takterzeugung
port (
gtakt: in std_logic;
takt: out std_logic;
ftakt: out std_logic;
reset: in std_logic
);
end component;
signal gtakt: std_logic;
signal takt: std_logic;
signal ftakt: std_logic;
signal reset: std_logic;
begin
ter: takterzeugung port map (gtakt, takt, ftakt, reset);
process
begin
gtakt <= '0';
wait for 500 ns;
gtakt <= '1';
wait for 500 ns;
end process;
end;
---------- takterzeugung_tb.vhd ---------
ok so now if i run cmd i do the following:
ghdl -a takterzeugung.vhd
ghdl -a takterzeugung_tb.vhd
ghdl -e takterzeugung_tb
till here no errors or anything. Now i want to run the testbench and output the signals into a vcd file:
ghdl -r takterzeugung_tb --stop-time=1000ms --vcd=takterzeugung_tb.vcd
the computer starts working and doesnt stop till ghdl advises to shut down the programm cause smthing went wrong.
The vcd-file is nearly empty and i cant view it with gtkwave.
So my heres my question:
What am i doing wrong? Is my vhdl code wrong? Do i need to add another command in cmd?
Thanks for your help in advance!