Help pls - constant value 0 / unconnected in block warning

[adibao]

Hi there.

I'm pretty new to VHDL and amongst others I need to realize serial communication between the fpga board (Digilent Nexys2) and the PC.
I've got the serial up running (not mine ofc) but I'm having a hard time storing the data. I need to receive for ex. 256 bits and when done send it back. That's not all of course, but for starters I want at least this to work.

So I've made something I think is a memory module(more like a fifo buffer), it's purpose is to receive and send back when 256 bits are received.
My problem is that I keep getting these warnings and I have no clue why:
Node <mem/Mram_ram> of sequential type is unconnected in block <main>.
Due to other FF/Latch trimming, FF/Latch <mem/addr_out_0> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process. (and so on)

Here's the code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.all;

entity memory_module is
	 generic(
			ADDR_WIDTH: integer:=8;
			DATA_WIDTH: integer:=8
	 );
    Port ( clk : in  STD_LOGIC;
            we : in  STD_LOGIC;
	    oe : in std_logic;
	    write_data : out std_logic;
	    din: in std_logic_vector(DATA_WIDTH-1 downto 0);
	    dout: out std_logic_vector(DATA_WIDTH-1 downto 0)
	 );
end memory_module;

architecture Behavioral of memory_module is
	type ram_type is array (2**ADDR_WIDTH-1 downto 0)
		of std_logic_vector(DATA_WIDTH-1 downto 0);
	signal ram: ram_type;
begin
	process (clk)
		variable addr_in: integer range 0 to 2**ADDR_WIDTH := 0;
		variable addr_out: integer range 0 to 2**ADDR_WIDTH := 0;
	begin
		if (clk'event and clk='1') then
			if (we='1') then
				ram(addr_in) <= din;
				addr_in := addr_in + 1;
			end if;
			if (addr_in = 256) then
				addr_in := 0;
				write_data <= '1';
			end if;
			--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=--
			if (oe='1') then
				dout <= ram(addr_out);
				addr_out := addr_out + 1;
			end if;
			if (addr_out = 256) then
				addr_out := 0;
				write_data <= '0';
			end if;
		end if;
	end process;
end Behavioral;

"we" comes from rx_done, "oe" from tx_done, and write_data goes to "tx_start".

Could someone please explain me why I get these warnings. I've tried std_logic_vector signals for addresses and to give them values in an upper module, but then I got "unconnected in block". I'm guessing I've got it all wrong somewhere, so a little help would be great. Thanks.