K
koyel.aphy
Hi,
Can someone tell what top.vhd is doing, which can be found in the list of vhdl codes in the following link
https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects/VHDL_Xilinx_Port
It appears to me that load always contain some undefined bits as it is undefined initially and rxdata fills only 8 bits (0 to 7) of load and further these 8 bits are transferred to the bits from 8 to 15 so ultimately only 0 to 15 will contain 1s or 0s and the rest will be undefined. If this happens state and data will contain undefined values and then how the code will work?
Thanks,
Regards
Can someone tell what top.vhd is doing, which can be found in the list of vhdl codes in the following link
https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects/VHDL_Xilinx_Port
It appears to me that load always contain some undefined bits as it is undefined initially and rxdata fills only 8 bits (0 to 7) of load and further these 8 bits are transferred to the bits from 8 to 15 so ultimately only 0 to 15 will contain 1s or 0s and the rest will be undefined. If this happens state and data will contain undefined values and then how the code will work?
Thanks,
Regards