Help with assert statement

[RishiD]

Hi,

I am attempting to write my first assert statements in my test bench.
I want the assert statements to run every clock cycle so I put them in
their own process. For some reason they don't seem to be working, the
first assert EWgreen = '1' and NSgreen = '1' always get triggered. But
according to the wave form it should not be triggered.

Does the syntax look good for the assert statements?

Thanks,

Rishi


PROCESS
BEGIN
CHECK_LOOP : LOOP

WAIT FOR 100 ns;

-- checks if any errors in traffic lights, giving go signals to both
sides at same time
assert (EWgreen = '1') and (NSgreen = '1') report "EWgreen and
NSgreen at same time" severity failure;
assert (EWgreen = '1') and (NSyellow = '1') report "EWgreen and
NSyellow at same time" severity failure;
assert (EWyellow = '1') and (NSgreen = '1') report "EWyellow and
NSgreen at same time" severity failure;
assert (EWyellow = '1') and (NSyellow = '1') report "EWyellow and
NSyellow at same time" severity failure;

-- checks to make sure crosswalk with walk signal given doesn't have
a green/yellow light on same street
-- severity is error only because this is a timing issue of the
constants in the traffic controller
assert (NSgreen = '1') and (NSpedwalk = '1') report "NSgreen and
NSpedwalk at same time" severity error;
assert (EWgreen = '1') and (EWpedwalk = '1') report "EWgreen and
EWpedwalk at same time" severity error;
assert (NSyellow = '1') and (NSpedwalk = '1') report "NSyellow and
NSpedwalk at same time" severity error;
assert (EWyellow = '1') and (EWpedwalk = '1') report "EWyellow and
EWpedwalk at same time" severity error;

END LOOP CHECK_LOOP;
END PROCESS;

 

[Ajeetha]

Hi Rishi,
Why not use concurrent assert? SImply move your asserts to
outside the process and you should be fine. However you may soon
realize that the basic, boolean level assertion capability of VHDL is
quite limited. New VHDL is considering adding PSL as part of it to make
it very powerful. Meanwhile the PSL-VHDL flavor provides all the
capabilities you need today! Also SVA + VHDL is picking up as well,
especially given the SystemVerilog interest among various design
houses.

HTH
Ajeetha, CVC
www.noveldv.com

 

[Andy]

The Assert will fire when the condition is false! i.e. you "assert
that the condition is true" therefore it warns you if it is not true
(false).

Andy

 

[RishiD]

Thanks for the two tips, will put them both into use.

Must have misread the assert statement description and wrote them
backwards.

Thanks guys.

RishiD