Help with frequency divider

[DaMeN]

I just started to learn VHDL and I realy need to write a program that hase 1 input and 1 output, the program hase to divide the input frequency by 4 and send it to the output.
I have couple of idias of how to do it but I wasnt able to write it.

entity NAME_OF_ENTITY is
     port (FreqIn: in std_logic;
             FreqOut: out std_logic);

end NAME_OF_ENTITY;

architecture architecture_name of NAME_OF_ENTITY is
    signal Freq: std_logic_vector (1 downto 0);
begin
if (rising_edge(FeqIn)) then
   Freq<=Freq+1;
end if;
if (Freq="11")
   FreqOut<="1"
   Freq<="00";
elsif (Freq\="11")
   FreqOut<="0";
end if;
end architecture_name;

This code does not work...
Please help

 

[i3igAnt]

This will work...

entity NAME_OF_ENTITY is
port (FreqIn: in std_logic;
FreqOut: out std_logic);
end NAME_OF_ENTITY;

architecture architecture_name of NAME_OF_ENTITY is
signal Freq: std_logic_vector (1 downto 0);
begin

if (rising_edge(FeqIn)) then
Freq<=Freq+1;
end if;

FreqOut <= Freq(1);

end architecture_name;

 

[i3igAnt]

Don't forget to include your process as well...

I missed this in the first post, you need a process statement for your counter.

process(FreqIn) is
begin
if rising_edge(FreqIn) then
Freq<=Freq+1;
end if;
end process;

FreqOut <= Freq(1);