help with serial to parallel conversion inside the fpga

[methi]

Hi..

I am working with xc3s400...my fpga takes in an input "MOSI" from a
microcontroller and another input "SCK"...

These 2 inputs r used for serial communication between the two
devices..

At this clock, "SCK" serial data is transferred to the FPGA through
"MOSI"...


Its an 8 bit value transferred serially

But this 8 bit value needs to be assigned to different variables inside
the FPGA..

So I was thinking tat i could use 2 successive 8 bit values, one
carrying an addr and one carrying the data information

So depending on this addr, the respective variables inside the fpga are
assigned values

I need to do this in vhdl...

Any suggestions or ideas are welcome...

Thank you,

Methi

 

[Andy Peters]

I am working with xc3s400...my fpga takes in an input "MOSI" from a
microcontroller and another input "SCK"...

These 2 inputs r used for serial communication between the two
devices..

At this clock, "SCK" serial data is transferred to the FPGA through
"MOSI"...

Its an 8 bit value transferred serially

But this 8 bit value needs to be assigned to different variables inside
the FPGA..

So I was thinking tat i could use 2 successive 8 bit values, one
carrying an addr and one carrying the data information

So depending on this addr, the respective variables inside the fpga are
assigned values

I need to do this in vhdl...

Any suggestions or ideas are welcome...

Sounds like an SPI interface, and your idea of sending an address byte
followed by a data byte will work fine -- in fact, I've done exactly
that.

I'd add a third signal. SPI slaves usually have a chip-select input.
You could use the chip select in two ways. One is to use it as a clock
enable and only allow shifting when the clock enable is asserted. The
other use is to use it as a register load signal; in other words, you
always shift on the appropriate edge of SCK, and you update your
registers on the assertion or deassertion of the chip select.

If the intent is to send one byte for address followed by a byte for
data, I'd use the latter mechanism -- simply decode the address to form
an enable for the chip select.

The VHDL? An exercise left for the reader.

-a