Help!!!

[gabriel]

Im combining three devices together using vhdl coding...a 0-192 counter(193 counts), a 0-11 counter(12 counts) and a bit pattern generator...so the program goes like this: once the 0-192 counter counts frm 0 to 192, it will reset itself to zero and the 0-11 will count one...this keeps on happening until the 0-11 counter reaches 11....then, both the 0-192 counter and 0-11 counters will reset to zero...well, iv programmed this part and its working perfectly..but the difficult part is when i have to include the bit pattern generator...which means having another output(Y) which will be set to '1' whenever the condition: (0-11 counter is at 2, 4, 5, 7, 8, 9 and the 0-192 counter shows 0)....otherwise output(Y) is '0'...anyone out there would like to enlighten me on this? pls? if u want to email me, my email is (e-mail address removed)...thank you very much in advance...this was the coding i did...


entity counter is
port (clk : in std_logic;
rst : in std_logic;
bitcnt : out std_logic_vector(7 downto 0);
framcnt : out_std_logic_vector(3 downto 0);
y : out std_logic);
end counter;

architecture rtl of counter is

signal q: std_logic_vector (7 downto 0);
signal x: std_logic_vector (3 downto 0);

begin process (clk, rst)
begin
if rst = '1' then
q<= "00000000";
x<= "0000";
y<='0';

elsif (clk = '1' and clk'event)
then if q<192 then
q = q +"1";
x<=x;

elsif(x=11 and clk='1' and clk'event)
then
q<= "00000000";
x<="0000";
else
x<=x+"1";
q<="00000000";

if (q=0)
then
if( x=2 or x=4 or x=5 or x=7 or x=8 or x=9)
then
y<='1';
else
y<='0';
end if;
end if;
end if;
end if;
end process;

bitcnt<=q;
framcnt<=x;
end rtl;

the prob with the program when i run it is that the output Y value has either got error or is alwaes set to zero...maybe i did nt do the "end if" or "elsif" correctly...but i dunnoe where im doing wrong...pls help me...