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Hi,
When I did the Post-Route Simulation of a pipelined floating point arithmetic unit using Modelsim, I am getting a warnings as follows:
# ** Warning: Design size of 135539 statements or 0 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
# Time: 0 ps Iteration: 0 Region: /test_bench_tbw File: test_bench_tbw.vhw
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf
# .main_pane.workspace.interior.cs.nb.canvas.notebook.cs.page2.cs
# .main_pane.signals.interior.cs
# ** Warning: /X_SFF SETUP High VIOLATION ON I WITH RESPECT TO CLK;
# Expected := 0.097 ns; Observed := 0.01 ns; At : 304.125 ns
# Time: 304125 ps Iteration: 3 Instance: /test_bench_tbw/uut/i_prenorm_addsub_fracta_28_o_0
Can anybody tell me what these warnings mean?
I am not getting the output for the first clock cycle in the post-route simulation. When I increase the period of the clock up to 200ns, output is coming correctly for the first clock cycle also. If, I go below 200 ns, output does not come in the first clock cycle and if I go below 100 ns, the output will not come for first two clock cycles. However, output is coming correctly in behavioral simulation in all the clock cycles.
Please throw some light.
Thanks...
Please help.
When I did the Post-Route Simulation of a pipelined floating point arithmetic unit using Modelsim, I am getting a warnings as follows:
# ** Warning: Design size of 135539 statements or 0 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
# Time: 0 ps Iteration: 0 Region: /test_bench_tbw File: test_bench_tbw.vhw
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf
# .main_pane.workspace.interior.cs.nb.canvas.notebook.cs.page2.cs
# .main_pane.signals.interior.cs
# ** Warning: /X_SFF SETUP High VIOLATION ON I WITH RESPECT TO CLK;
# Expected := 0.097 ns; Observed := 0.01 ns; At : 304.125 ns
# Time: 304125 ps Iteration: 3 Instance: /test_bench_tbw/uut/i_prenorm_addsub_fracta_28_o_0
Can anybody tell me what these warnings mean?
I am not getting the output for the first clock cycle in the post-route simulation. When I increase the period of the clock up to 200ns, output is coming correctly for the first clock cycle also. If, I go below 200 ns, output does not come in the first clock cycle and if I go below 100 ns, the output will not come for first two clock cycles. However, output is coming correctly in behavioral simulation in all the clock cycles.
Please throw some light.
Thanks...
Please help.