hlp_needed in VHDL

[vicky]

Hi All,

i'm new to VHDL, my aim is to overload airthmatic and shift operators
for STD_LOGIC_VECTORs/STD_LOGICs.

I'm confused which library package i should consult, wether to use
STD_LOGIC_SIGNED or STD_LOGIC_UNSIGNED. what's the nature of
STD_LOGIC_VECTOR, How it behaves i.e. SIGNED or UNSIGNED??.

Waiting for early response.

 

[Neo]

If your requirement dosent operate on signed numbers then go for
unsigned else use signed. std_logic_vector dosent have any numerical
properties so you have to use one of the above to interpret them as
representation of numbers.

 

[Martin Thompson]

Hi All,

i'm new to VHDL, my aim is to overload airthmatic and shift operators
for STD_LOGIC_VECTORs/STD_LOGICs.

They are already there in numeric_std, just use the unsigned or signed
data types, depending on the type of data you are using.

SLVs have no numerical representation (although we sometimes pretend
that they do!)

Cheers,
Martin

 

[Jim Lewis]

Vikas,

i'm new to VHDL, my aim is to overload airthmatic and shift operators
for STD_LOGIC_VECTORs/STD_LOGICs.

Don't do this. Shift operators are planned to be added in
the next revision of VHDL. Let your vendor know that you
want this feature supported (we need their funding to support
our standards work).

For now, use concatenation for shifting:

signal ShiftLeft, uShiftRight, sShiftRight, A : std_logic_vector(7 downto 0) ;
signal ShiftInVal : std_logic ;

ShiftLeft <= A(6 downto 0) & '0' ;
uShiftRight <= '0' & A(7 downto 1) ; -- unsigned
sShiftRight <= A(7) & A(7 downto 1) ; -- signed


In general I prefer concatenation as it allows me also to shift
something in while shifting a direction:
ShiftLeft <= A(6 downto 0) & ShiftInVal ;

It also works for arrays of arrays.

I'm confused which library package i should consult, wether to use
STD_LOGIC_SIGNED or STD_LOGIC_UNSIGNED. what's the nature of
STD_LOGIC_VECTOR, How it behaves i.e. SIGNED or UNSIGNED??.

My rules are:
For all new designs
* use the types signed and unsigned from package numeric_std
for math operations.
* package std_logic_unsigned and std_logic_vector may be used
for testbenches that apply algorithms to non-numeric types
(such as incrementing address).
* When I am lazy, I will use std_logic_unsigned for
incrementers/decrementers
* Never use std_logic_signed. If you mean signed, you are clearly
doing math and should be using the type signed because of the value
of it documenting your design.

** note, use numeric_std_unsigned for new designs once it is
standardized.

** note some who follow a more rigorous design methodology, forbid
the use of std_logic_unsigned and math with std_logic_vector.
In this case you would use types unsigned or signed and use
type conversions (mainly similar to casting) where necessary.


For updating older designs
* Try to stay consistent with the packages that that design uses.
Use std_logic_arith only if it is used in the rest of the design,
otherwise, use numeric_std as noted for new designs.


Best Regards,
Jim
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