How to describe this block diagram in VHDL?

[pitarda]

I am new at VHDL and would like to get familiar with it

I would like to describe this Pulse Width Modulator and just can't
figure it out.

The description found on the net:

"Basic principle: a register to store the value which is loaded on to
the Up/Down Counter whenever the counter reaches its terminal count.
The terminal counter is used to generate the pulse width modulation
A data register: to store the value for the counter.Value determines
the pulse width. The Up/Down Counter: loaded with a new value from the
data register when the counter reaches its terminal count.Toggle
Flip-flop generates the PWM output.
When data value is first loaded, counter counts down from data value to
0. Terminal count and PWM signals are Low. When counter goes through 0
transition, terminal count is generated.
Triggers Toggle Flip-flop to drive PWM signal High. Data value is
re-loaded and counting proceeds up to maximum value. Terminal count
generated again when counter reaches its maximum value. Drives PWM
signal to toggle from High to Low. Data value is re-loaded and cycle
repeats.
Direction of counter controlled by PWM signal: counter is set to count
down when PWM is Low, and count up when PWM is High. Terminal count
controls data value loaded to counter from data register. Data is
loaded when terminal count is High. Duty cycle of the PWM signal is
controlled by data value loaded to the up/down counter. Higher the data
value, higher the duty cycle."

And the block diagram can be found here:

http://freeweb.siol.net/pitarda/vhdl.jpg

I would really be thankful to anyone who would take some time to write
it.

So far I managed to write my own PWM generator but I have some problems
with it and would just like to describe this one.

Thanks

 

[Frank Buss]

I am new at VHDL and would like to get familiar with it

I would like to describe this Pulse Width Modulator and just can't
figure it out.

The description found on the net:

So you don't want to write it yourself, but you want the VHDL source code
for it? Maybe you entered the wrong search string?

http://www.google.com/search?q=pwm+filetype:vhd

 

[pitarda]

Thanks for your reply.

I have written about ten different versions of PWM in my own way. It
does work. It's a clumsy code, but it works. There are also quite a lot
of of them on the net, but I would also like to see an example of how a
block diagram like this one, can be described in VHDL. That's it. It's
not that I don't want to write a code. I want to learn something. And
learning by example has been my best way to figure out how things work.




Frank Buss je napisal:

 

[Paul Uiterlinden]

I am new at VHDL and would like to get familiar with it

Then start digging in http://www.vhdl.org/
And don't forget the FAQ: http://www.vhdl.org/comp.lang.vhdl/

I would like to describe this Pulse Width Modulator and just can't
figure it out.

And what is it that you cannot figure out?
What have you tried?

If you actually want to follow the block diagram, implement the blocks
as separate entity/architecture pairs. Make the top level by
declaring the components, instantiate them and connect them.

 

[Frank Buss]

but I would also like to see an example of how a
block diagram like this one, can be described in VHDL. That's it. It's
not that I don't want to write a code. I want to learn something. And
learning by example has been my best way to figure out how things work.

Yes, learning by example is the second best method to learn something.
Writing your own code is the best method

The description is very hardware low-level, so a VHDL implementation is
straight forward and I would write it like this:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity pwm is
generic(
terminal_count : positive := 255);
port(
reset : in std_logic;
clock : in std_logic;
data : in natural range 0 to terminal_count := 200;
output : out std_logic);
end entity pwm;

architecture rtl of pwm is

signal output_register : std_logic := '0';
signal counter : natural range 0 to terminal_count := 0;

begin

pwm: process(clock)
begin
if reset = '1' then
output_register <= '0';
counter <= 0;
elsif rising_edge(clock) then
if counter = terminal_count then
counter <= data;
output_register <= not output_register;
else
if output_register = '1' then
counter <= counter + 1;
else
if counter = 0 then
counter <= terminal_count;
else
counter <= counter - 1;
end if;
end if;
end if;
end if;
end process;

output <= output_register;

end architecture rtl;