How to draw Logic Network from VHDL code

[wave00]

Could someone help me how to draw the devices of the network from the vhdl
code.
An example at this link

http://home.dei.polimi.it/bolchini/didattica/esami/RLA_20080211cb.pdf

last exercise

 

[Frank Buss]

Could someone help me how to draw the devices of the network from the vhdl
code.
An example at this link

http://home.dei.polimi.it/bolchini/didattica/esami/RLA_20080211cb.pdf

last exercise

I can do the homework for you, but only if you tell this your instructor
and if I would get the certificate for it

 

[Jonathan Bromley]

Could someone help me how to draw the devices of the
network from the vhdl code.
An example at this link

http://home.dei.polimi.it/bolchini/didattica/esami/RLA_20080211cb.pdf

last exercise

Hmmm... That exercise carries 20% of the marks for a 2 hour paper.
So you should be able to do it in 24 minutes - let's say 20 minutes
to leave a little time for checking. And, amongst other (easier)
things, it asks you to draw the logic diagram of a 4*4-bit
multiplier using only gates and multiplexers. I wonder how long
it took the writer of the question to create the model answer?

The model also has some errors that would prevent it from
compiling, and at least one error that would be detected
at runtime in simulation (but probably at compilation by a
synthesis tool). Extra marks for locating those

Anyway, now that you're away from the exam. room, you can
simply take the code, fix it, run it through synthesis and
look at the RTL schematic. At least that would introduce
a measure of realism to the exercise, something that the
person who set the paper seems to have lacked.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Frank Buss]

Hmmm... That exercise carries 20% of the marks for a 2 hour paper.
So you should be able to do it in 24 minutes - let's say 20 minutes
to leave a little time for checking. And, amongst other (easier)
things, it asks you to draw the logic diagram of a 4*4-bit
multiplier using only gates and multiplexers. I wonder how long
it took the writer of the question to create the model answer?

It should be not too difficult. You have to use only gates, multiplexers
and flip-flops, but this doesn't mean that you can't create your own
symbols for half-adders etc. with the basic gates, from which you can build
the multiplier (e.g.
http://groups.google.de/group/comp.lang.vhdl/msg/32a9a02c2b2b838d ). You
have to know the basic ciruits and ideas, but then it should be possible to
draw it in some minutes.

The model also has some errors that would prevent it from
compiling, and at least one error that would be detected
at runtime in simulation (but probably at compilation by a
synthesis tool). Extra marks for locating those

And you can't fix this, because of the bad coding style (complete lack of
any comments) you can't know which bits are needed from the multiplication
result. Formatting is not very consistent, too, sometimes spaces after
superfluously parantheses, sometimes not. Looks like an inexperienced VHDL
programmer has written the code.