how to generate blockdiagram

[chisti09]

i am having simple code in VHDL,
i am runing this in active hd 6.1,

the how to generate block diagram automatically for the given code
sir.

i.e this code is cascade of 3 flip-flops, so software to genetate
this

entity rsynch is
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
d : in STD_LOGIC;
q : buffer STD_LOGIC
);
end rsynch;

--}} End of automatically maintained section

architecture arch_rsynch of rsynch is
signal temp1 : std_logic;
signal temp2 : std_logic;
begin
p1: process ( reset,clk)
begin
if reset = '1' then
q <= '0';
elsif (clk'event and clk ='1' ) then
temp1 <= d;
temp2 <= temp1;
q <=temp2;
end if ;
end process p1;

end arch_rsynch;

 

[Mike Treseler]

the how to generate block diagram automatically for the given code

I would use the ise or quartus rtl viewer.

-- Mike Treseler

 

[Mark McDougall]

I would use the ise or quartus rtl viewer.

Having seen what comes out of Quartus RTl viewer, I wouldn't!

Regards,

 

[gzidude]

Mark,
I know what you mean. However, I have seen that a lower level description looks fine on an RTL viewer. High level code looks pretty bad though. The code given above shouldn't look too bad.

 

[Mike Treseler]

Having seen what comes out of Quartus RTl viewer, I wouldn't!

http://home.comcast.net/~mike_treseler/stack.pdf

looks ok to me

 

[Mark McDougall]

looks ok to me

I haven't had much luck with my designs!

Regards,