How to generate serial random data pattern ?

[C T]

For the testbench, I would like to send a serial random data pattern
(16-bit words, 10MHz clock) via a FPGA to a 512K16 RAM and then later
on read the data back for verification.

Please let me know what the best approach in VHDL coding to come up
with the pattern generation and verification should be.

Thanks.

Calvin

 

[Amontec Team]

For the testbench, I would like to send a serial random data pattern
(16-bit words, 10MHz clock) via a FPGA to a 512K16 RAM and then later
on read the data back for verification.

Please let me know what the best approach in VHDL coding to come up
with the pattern generation and verification should be.

Thanks.

Calvin

Use pseudo-random -> a shift register and an XOR in the MSB-LSB feedback.

Laurent www.amontec.com

 

[Cameron, Charles B.]

For the testbench, I would like to send a serial random data pattern
(16-bit words, 10MHz clock) via a FPGA to a 512K16 RAM and then later
on read the data back for verification.

Please let me know what the best approach in VHDL coding to come up
with the pattern generation and verification should be.

Thanks.

Calvin

There's a good description of linear feedback shift registers at


http://www.newwaveinstruments.com/r...uence_linear_feedback_shift_register_lfsr.htm

Charles B. Cameron

 

[Charles M. Elias]

For the testbench, I would like to send a serial random data pattern
(16-bit words, 10MHz clock) via a FPGA to a 512K16 RAM and then later
on read the data back for verification.

Please let me know what the best approach in VHDL coding to come up
with the pattern generation and verification should be.

Thanks.

Calvin

Calvin

Ben Cohen's website has a very nice package that allows you to create
linear-feedback shift registers (LFSRs) of many lengths. These
generate a pseudorandom sequence that may work for you.

http://members.aol.com/vhdlcohen/vhdl is the link.

I have used LFSRs in testbenches and in designs. For simulations I
have also used a random number generation procedure which produces an
integer which I then convert to std_logic_vector or unsigned or
whatever:

signal Seed_s : natural := 17654; --you may pick other values for the
seed

procedure RandUnsigned( Size : in natural;
signal Seed : inout natural;
signal RandVec : out unsigned ) is

variable Modulus : integer := ( 2 ** Size ) - 1;
constant Multiplier_c : INTEGER := 25173;
constant Increment_c : INTEGER := 13849;

begin
Seed <= ( Multiplier_c * Seed + INCREMENT_c ) mod Modulus;
RandVec <= To_Unsigned( Seed, Size );
end procedure RandUnsigned;

procedure RandSLV( Size : in natural;
signal Seed : inout natural;
signal RandVec : out std_logic_vector )
is

variable Modulus : integer := ( 2 ** Size ) - 1;
constant Multiplier_c : INTEGER := 25173;
constant Increment_c : INTEGER := 13849;

begin
Seed <= ( Multiplier_c * Seed + INCREMENT_c ) mod Modulus;
RandVec <= std_logic_vector(To_Unsigned( Seed, Size ));
end procedure RandSLV;

Each time you call the procedure the vector output takes on a new
"random" value.

Charles