how to implement this c++ algorithm in vhdl

[niyander]

Hello,
I would really appreciate if some one can tell me how to implement the
following c++ algorithm in VHDL.

for(int x = 0; x < n; x++)
{
double ca = -1.0;
double sa = 0.0;
int l1 = 1, l2 = 1;
for(int l=0;l < l2n;l++)
{
l1 = l2;
l2 *= 2;
double u1 = 1.0;
double u2 = 0.0;
for(int j = 0; j < l1; j++)
{
for(int i = j; i < n; i += l2)
{
int i1 = i + l1;
double t1 = u1 * *(GRe + m * x + i1) - u2 * *(GIm + m * x +
i1);
double t2 = u1 * *(GIm + m * x + i1) + u2 * *(GRe + m * x +
i1);
*(GRe + m * x + i1) = *(GRe + m * x + i) - t1;
*(GIm + m * x + i1) = *(GIm + m * x + i) - t2;
*(GRe + m * x + i) += t1;
*(GIm + m * x + i) += t2;
}
double z = u1 * ca - u2 * sa;
u2 = u1 * sa + u2 * ca;
u1 = z;
}
sa = sqrt((1.0 - ca) / 2.0);
if(!inverse) sa = -sa;
ca = sqrt((1.0 + ca) / 2.0);
}
}

thanks

 

[Kenn Heinrich]

Some C programmers really need to adjust their
medication. If you want a 2-dimensional array,
why the hell can't you ask for one and let the
compiler figure out how to do the subscripts?
Pointer arithmetic as complicated as that is
just sick.

Because it's clearly more efficient! Don't you know that square brackets
cost at least twice as much as asterisks and plus signs? And, to boot,
that's the way all of the FORTRAN numerical code looked thirty years
ago, so it must be good, right? Sigh.

This is the same school of "optimization" that prevents people from
seeing over the walls of their cubes unless they're given a separate
component declaration and a std_logic_vector to look for. Packages?
Records? Functions? Vade retro, satana!!!

Luckily you can't do it in VHDL,
so you need to use a proper array. Perhaps
you could be kind enough to offer us the
algorithm in a less vomit-provoking form.

But seriously, Jonathan has a good point. Your request doesn't make sense
for the following reason:

In a "software" language like C, in many ways, a straightforward
algorithm can often be directly coded in the implementation language
itself in terms ONLY of the data flow. This is what was provided.

In the hardware world, you usually need to first design the data flow
algorithm in terms of time steps, buffers, clock cycles, intermediate
registers, and so forth. Only after you have turned the algorithm into a
data flow engine on paper, then you code the engine in the
implementation language (VHDL). It doesn't make sense to try to skip
the design step in hardware except for the simplest, one-line, code
examples.

Nobody here can do a sensible job with your design without doing a lot
of work and understanding the fundamental behaviour and limits of the
algorithm.

On the flip side, if you only want this for simulation purposes, you're
probably better off using a foreign-function-interface in your simulator
to call the original C code than to recode the C into non-synthesizable
VHDL.

- Kenn

 

[Mark McDougall]

Because it's clearly more efficient! Don't you know that square brackets
cost at least twice as much as asterisks and plus signs?

I'm not sure where _you_ buy your operators from, but I've always found
asterisks are more expensive because of the crinkly edges...

Regards,