How to introduce delay in Structural description ?

[priya]

Hi all,

The follwing code is simple 2-input and gate model.
Here I am having doubt.


begin
t1 : and4 port map ( in1, in2, out1 );
t2 : and_output port map ( out1,out2);

end and_arch ;


I know these two instance t1,t2 will be executed concurrently at 0 ns
simulation time.But here T1 instance will execute at 0ns simulation
time.t2 instance will execute after updated the value from out1.So Here
I need to introduce some delay to execute the t2 instance at some
simulation time.

How to introduce delay at instance t1? Give me some ideas to proceed
further?

regards,
priya




------------------------------------------------
entity and4 is
port ( in1, in2 : in bit;
out1 : out bit );
end;
architecture only of and4 is
begin
out1<=in1 and in2;
end;
-----------------------------------------
entity and_output is
port ( out1 : in bit;
out2 : out bit
);
end;
architecture out_arch of and_output is
begin
out2<=out1;
end;
-- -- -- -----------------------

library STD;
use STD.TEXTIO.all;
entity testbench is
end testbench;
architecture and_arch of testbench is
component and4
port ( in1, in2 : in bit;
out1 : out bit
);
end component;
component and_output
port ( out1: in bit;
out2: out bit
);
end component;
signal in1 : bit;
signal in2 : bit;
signal out1 : bit;
signal out2 : bit;
begin
t1 : and4 port map ( in1, in2, out1 );
t2 : and_output port map ( out1,out2);

end and_arch ;

 

[Mike Treseler]

How to introduce delay at instance t1?

If you mean for simulation, delta delays
are already built into the language.

If you mean a synthesized delay, you need
to describe a counter or shift register.

-- Mike Treseler

 

[priya]

Thanks Mike...

I meant it for Simulation Delay.I want to give extra delay for
instance t2 module.

For example In Verilog we can give delay when the module
instantiation

for eg...and #(3) gate1 (out1, in1, in2);

My question is How can we add the delay statement in VHDL while
module instantiation.

 

[Ralf Hildebrandt]

I meant it for Simulation Delay.I want to give extra delay for
instance t2 module.

For example In Verilog we can give delay when the module
instantiation

for eg...and #(3) gate1 (out1, in1, in2);

My question is How can we add the delay statement in VHDL while
module instantiation.

What about mapping the output to a dummy signal and a wait statement,
that copies the value from the dummy to the real output?

t1 : and4 port map ( in1, in2, outdummy);

process(outdummy)
begin
wait for 1 ns;
out1<=outdummy;
end process;

It introduces a little bit more code, but this should not be a problem,
because modifications have to be done anyway.

Ralf