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VHDL
How to introduce delay in Structural description ?
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[QUOTE="priya, post: 142798"] Thanks Mike... I meant it for Simulation Delay.I want to give extra delay for instance t2 module. For example In Verilog we can give delay when the module instantiation for eg...and #(3) gate1 (out1, in1, in2); My question is How can we add the delay statement in VHDL while module instantiation. [/QUOTE]
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How to introduce delay in Structural description ?
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