How to perform a timing simulation in Modelsim with QuartusII output file ?

[ALuPin]

Hi newsgroup people,

I want to perform a timing simulation of an SRAM controller with
Modelsim (version Altera 5.7e) .
The background: With address, data and write strobe all changing
simultaneously, I am not sure whether the right data will get written
to the right location in the SRAM.

Right now I am performing a functional simulation. Since I am running
with timing check off, data should never be corrupted.

Since the SRAM controller is a central module in my design I have to
know exactly whether it will run correctly or not so that other
modules adapted to the controller will not have to be modified
belatedly.

It is for that purpose of operating on a boundary condition that I
want to add timing to my simulation to get a better idea of what will
happen in hardware.
I am working with Altera QuartusII software (version 4.0 SP1).

For the purpose of a timing simulation under Modelsim I would like to
know how to make settings in QuartusII to get the correct output files
and how to include them in Modelsim.

I would appreciate if you had the time to have a closer look at
http://mitglied.lycos.de/vazquez78

Thank you very much for your help.

 

[Mike Treseler]

ALuPin wrote

I want to perform a timing simulation of an SRAM controller with
Modelsim (version Altera 5.7e).

The normal way to do this is to replace
your synthesis code instance with an instance of
the place+route vhdl netlist (.vho for altera).
The modelsim website shows detailed examples.

Note that you can't do this until you have
testbench code that works with your synth code.

Note that a timing sim is not strictly
needed for a synchronous design that
meets static timing after place and route.

The background: With address, data and write strobe all changing
simultaneously, I am not sure whether the right data will get written
to the right location in the SRAM.

Your write cycle won't work if those signals are all
changing at the same time.
I expect that you don't have a complete funtional testbench yet.

Right now I am performing a functional simulation. Since I am running
with timing check off, data should never be corrupted.

Look at the modelsim waveforms.
Does your functional testbench do writes and reads to the SRAM model ok?
Does it handle walking address and data bit tests?

I am working with Altera QuartusII software (version 4.0 SP1).

For the purpose of a timing simulation under Modelsim I would like to
know how to make settings in QuartusII to get the correct output files
and how to include them in Modelsim.

All you need out of quartus is the .vho file and
the vhdl device models to compile with modelsim.

I would appreciate if you had the time to have a closer look at
http://mitglied.lycos.de/vazquez78

You may be confused about the Quartus simulation options.
Ignore this. Quartus can *not* do VHDL simulations. Modelsim can.

-- Mike Treseler

 

[ALuPin]

Note that you can't do this until you have
testbench code that works with your synth code.

I have testbench code for functional simulation. Writing to and reading
from the SRAM seems to be ok.
Do you mean that testbench code for timing simulation should be different?

Note that a timing sim is not strictly
needed for a synchronous design that
meets static timing after place and route.

But there is an asynchronous SRAM ...

Your write cycle won't work if those signals are all
changing at the same time.
I expect that you don't have a complete funtional testbench yet.

Yes I have.
Did you look at the SRAM specification. If we believe it there you
be no problem about that. But I am not sure.

 

[ALuPin]

Hi again,

I have tried the following:


1. I compile the .vho file
2. I compile the testbench
3. Choose Simulate (Simulate menu)
4. CLick the SDR tab and click ADD
5. Specify the location of the SDF file and click ok
6. In the library list (Design tab) I specify the testbench
as top-level-file
7. Click ADD (Resolution ps)
8. Click LOAD


But then I get the error message:
# ** Fatal: SDF files require Altera primitive library
# Time: 0 fs Iteration: 0 Instance: /tb_simu_sram_ctrl_sie File:
F:/TIMING_SIMULATION/Sram_ctrl/simulation/modelsim/tb_simu_sram_ctrl_sie.vhd
# FATAL ERROR while loading design
# Error loading design

But there already is a precompiled cyclone library in the Modelsim
Workspace
with Path: modelsim_work

So why do I get this warning?

Rgds

 

[Mike Treseler]

ALuPin wrote

But there is an asynchronous SRAM ...

Consider designing a synchronous controller
for your asynchronous SRAM.

Did you look at the SRAM specification.

No, but I expect that any SRAM requires
a few nanoseconds of address and data
setup time before the write strobe.

-- Mike Treseler

 

[Mike Treseler]

ALuPin wrote

But there is an asynchronous SRAM ...

Consider designing a synchronous controller
for your asynchronous SRAM.

Did you look at the SRAM specification.

No, but I expect that any SRAM requires
a few nanoseconds of address and data
setup time before the write strobe.

-- Mike Treseler

 

[Mike Treseler]

But then I get the error message:
# ** Fatal: SDF files require Altera primitive library
# Time: 0 fs Iteration: 0 Instance: /tb_simu_sram_ctrl_sie File:
F:/TIMING_SIMULATION/Sram_ctrl/simulation/modelsim/tb_simu_sram_ctrl_sie.vhd

But there already is a precompiled cyclone library in the Modelsim
Workspace with Path: modelsim_work

It may be compiled, but it is not mapped to your work directory.
Read up on vmap, vcom, and vsim -sdfmax.
Consider using the vsim command line instead of the GUI.

-- Mike Treseler

 

[ALuPin]

It may be compiled, but it is not mapped to your work directory.
Read up on vmap, vcom, and vsim -sdfmax.
Consider using the vsim command line instead of the GUI.

-- Mike Treseler

It may be compiled, but it is not mapped to your work directory.
Read up on vmap, vcom, and vsim -sdfmax.
Consider using the vsim command line instead of the GUI.

-- Mike Treseler

1. Do you mean the Altera primitives library "altera_mf" ?

2. I tried the following in Modelsim:

File ---> New ---> Library ---> a map to an existing library --->
Libray Name : altera_mf; Library maps to: modelsim_work


When I click OK I get the error message:
" A library altera_mf already exists; it is mapped to
$MODEL_TECH/../altera/vhdl/altera_mf.
The map must be deleted before a new library can be created. "

What do I have to do?

Thank you for your help.

Kind regards

 

[Mike Treseler]

ALuPin wrote

I tried the following in Modelsim:

File ---> New ---> Library ---> a map to an existing library --->
Library Name : altera_mf; Library maps to: modelsim_work
When I click OK I get the error message:
" A library altera_mf already exists; it is mapped to
$MODEL_TECH/../altera/vhdl/altera_mf.
The map must be deleted before a new library can be created. "

What do I have to do?

You can look this stuff up on the vendor sites as well as I can.
I can't tell you what to "click" on, because I don't use
the modelsim gui. Call Altera or Mentor support for that.

I think your time would be better spent
an a synchronous design that does not
require the annoyances of a back-annotated sim.

The error message is telling you that you are missing
a USE clause with the mapped directory name altera_mf
at the top of your testbench.

The format is

USE Mapped_dir_name.VHDL_package_name.all

For a separate directory, maybe something like:

use altera_mf.altera_mf_components.all

For the work directory, maybe something like:

use work.altera_mf_components.all


-- Mike Treseler

 

[ALuPin]

Hi,

I am able to arrange a timing simulation now.

The results I see do not show what I exptected.

I do not know what to think about it.
The problem is that there is some synchronous design in my FPGA (SRAM
controller) and an external asynchronous SRAM.

How can I get reliable simulation results? Is such a timing simulation
somehow dangerous to trust in ?

I would appreciate your advice because right now I am very confused.

Thank you in advance.

 

[Mike Treseler]

LuPin wrote

I am able to arrange a timing simulation now.
The results I see do not show what I expected.

Is the stimulus what you expect?
Is clock and reset running?
Is the block ram working?
Is the model for the external RAM hooked up right?
Is your testbench wiggling the pins
on your external ram just like it shows on
the device data sheet?

I do not know what to think about it.
The problem is that there is some synchronous design in my FPGA (SRAM
controller) and an external asynchronous SRAM.
How can I get reliable simulation results?

It starts with a reliable design.
For me today, this means 100% synchronous processes
and inferred FPGA RAM, ROM, counters, shifters etc.
No wizards or code generators, just code.

The design function is verified with a synchronous vhdl testbench.
The design timing is verified by place+route static timing
and requires *no* testbench at all.

Is such a timing simulation somehow dangerous to trust in ?

Not dangerous, but it's fancy frosting for a
cake you don't have yet.

I would appreciate your advice because right now I am very confused.

There are no easy answers.
Reread this whole thread.
Consider starting fresh and working a
small part of the design all the way
through simulation and static timing.
Then add another part and repeat.

Or try something else.

-- Mike Treseler

 

[ALuPin]

Is your testbench wiggling the pins

on your external ram just like it shows on
the device data sheet?

Thank you for your advice.
One more question: What do you mean with "wiggling the pins" ?

Best regards

 

[ALuPin]

Is your testbench wiggling the pins

on your external ram just like it shows on
the device data sheet?

Thank you for your advice.
One more question: What do you mean with "wiggling the pins" ?

Best regards

 

[mouna]

Error simulation

Hello;

I face the same pb when i try to run an EDA gate level simulation,
I don't understand the solution, what must i do to solve the problem below:

** Fatal: SDF files require Altera primitive library
# Time: 0 ps Iteration: 0 Instance: /test_mm File: D:/THESE/INRIA/FPGA_2s180/VGA/4PE_avecVGA/avec_Xnet_and_linear/test_mm.vhd Line: UNKNOWN
# FATAL ERROR while loading design

Please help me;

Hi,

I am able to arrange a timing simulation now.

The results I see do not show what I exptected.

I do not know what to think about it.
The problem is that there is some synchronous design in my FPGA (SRAM
controller) and an external asynchronous SRAM.

How can I get reliable simulation results? Is such a timing simulation
somehow dangerous to trust in ?

I would appreciate your advice because right now I am very confused.

Thank you in advance.