how to start post synthesis simulation

[sagar g]

hello everyone,
I'm a newbie to vhdl getting trained as a vhdl design engineer,
I've given a task to implement a SDI-12 protocol and show post synthesis simulation results.
I've written vhdl code and testbench for the protocol, it works fine in pre-synthesis simulation, what is the next step to start post synthesis simulation please help
I have Xilinx ISE 14.2 and Libero v9.1 in which tool shall I start and how to do it. please help in step wise procedure
thanks in advance

 

[pontus.stenstrom]

I've written vhdl code and testbench for the protocol, it works fine in pre-synthesis simulation, what is the next step to start post synthesis simulation please help
Great, you start "the right" way, code and TB.

I have no experience with your tools, but normally now you need to run synt
and have that tool to export a [vhdl] netlist of the result. That netlist will
typically connect a lot of primitives together - primitives from the tech lib
in question. You need to have that library compiled and library mappings that
points there.
Compiling the netlist and getting everything together may be tricky,
try with a very simple design to start with.

If you use std_logic and std_logic_vector for you top level entity ports, your
synt tool will probably produce something that fits right into your tb.
Otherwise you can either write a wrapper around the synt result, or modify your
source. Then instantiate the synt result in place of the DUT (your SDI-12).

When you get the taste of this, look into VHDL configurations. This is a
specific "setup" of an entity (the TB), specifying alternative mapping between
entities below and which library units/architectures to hook in to.
You need to do a "component instantiation" in your tb instead of a "entity instantiation" (of the DUT in the TB) to be able to use configurations.

HTH -- Pontus