I'm a newbie to VHDL,
Seeking help to display to LED.
I've stored 8 bits value into ROM (a distributed memory) core.
I've declared the conponent in architechture:
component LED_DISTMEM
port (
a: IN std_logic_VECTOR(11 downto 0);
spo: OUT std_logic_VECTOR(7 downto 0));
end component;
I've instantiated in begin
LED_DISTMEM_ins : LED_DISTMEM
port map (
a => a,
spo => spo);
when I have an input at a, i'll take the spo to display on LED.
---so i've written:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity LED_Display is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
START_LED :in std_logic;
LED : out STD_LOGIC_VECTOR (7 downto 0));
end LED_Display;
-------------------------------------------------------------
----------------------------------------------------
architecture LED_DISP_ARC of LED_Display is
component LED_DISTMEM
port (
a: IN std_logic_VECTOR(11 downto 0);
spo: OUT std_logic_VECTOR(7 downto 0));
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of LED_DISTMEM: component is true;
---------
begin
LED_DISTMEM_ins : LED_DISTMEM
port map (
a => a,
spo => spo);
signal spo_temp : std_logic_Vector (7 downto 0);
begin
codingrocess (CLK,RST)
begin
if RST = '1' then
LED<= "00000000";
elsif (CLK'event and CLK = '1') then
if (START_LED ='1') then
LED<= spo_temp;
end if;
end if;
mapping rocess (CLK,spo_temp)
begin
if RST = '1' then
LED<= "00000000";
elsif (CLK'event and CLK = '1') then
spo<=spo_temp;
end if;
end if;
end process;end LED_DISP_ARC;
--Is this correct?
--THanks!
Seeking help to display to LED.
I've stored 8 bits value into ROM (a distributed memory) core.
I've declared the conponent in architechture:
component LED_DISTMEM
port (
a: IN std_logic_VECTOR(11 downto 0);
spo: OUT std_logic_VECTOR(7 downto 0));
end component;
I've instantiated in begin
LED_DISTMEM_ins : LED_DISTMEM
port map (
a => a,
spo => spo);
when I have an input at a, i'll take the spo to display on LED.
---so i've written:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity LED_Display is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
START_LED :in std_logic;
LED : out STD_LOGIC_VECTOR (7 downto 0));
end LED_Display;
-------------------------------------------------------------
----------------------------------------------------
architecture LED_DISP_ARC of LED_Display is
component LED_DISTMEM
port (
a: IN std_logic_VECTOR(11 downto 0);
spo: OUT std_logic_VECTOR(7 downto 0));
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of LED_DISTMEM: component is true;
---------
begin
LED_DISTMEM_ins : LED_DISTMEM
port map (
a => a,
spo => spo);
signal spo_temp : std_logic_Vector (7 downto 0);
begin
codingrocess (CLK,RST)
begin
if RST = '1' then
LED<= "00000000";
elsif (CLK'event and CLK = '1') then
if (START_LED ='1') then
LED<= spo_temp;
end if;
end if;
mapping rocess (CLK,spo_temp)
begin
if RST = '1' then
LED<= "00000000";
elsif (CLK'event and CLK = '1') then
spo<=spo_temp;
end if;
end if;
end process;end LED_DISP_ARC;
--Is this correct?
--THanks!