how to use dual behavior?

[raullim7]

i have 3 processes in my code, all running with a shared counter.

counter counts from 0 to 99.
process1(rising edge)
take in a sample at the rising edge, so in total i will have 100
samples.

process2(falling edge)
take in a sample at the falling edge, so in total i will have another
100 samples.

process3(rising edge)
add up the samples for the previous 2 processes.

i have a problem here. how can i add the samples in dual edge form as
i am only able to add them during the rising edge in process3. my
output will be 1,3,5,7,9..etc.. my desired output is 1,2,3,4,5...etc..
i cant use a process4 to since it will only give me 2,4,6,8.. etc..

is there anyways that i do to get my output as 1,2,3,4,5,6... pls
help.. thanks

 

[raullim7]

i have 3 processes in my code, all running with a shared counter.

counter counts from 0 to 99.
process1(rising edge)
take in a sample at the rising edge, so in total i will have 100
samples.

process2(falling edge)
take in a sample at the falling edge, so in total i will have another
100 samples.

process3(rising edge)
add up the samples for the previous 2 processes.

i have a problem here. how can i add the samples in dual edge form as
i am only able to add them during the rising edge in process3. my
output will be 1,3,5,7,9..etc.. my desired output is 1,2,3,4,5...etc..
i cant use a process4 to since it will only give me 2,4,6,8.. etc..

is there anyways that i do to get my output as 1,2,3,4,5,6... pls
help.. thanks

problem solved... thanks for your attention..

 

[raullim7]

problem solved... thanks for your attention..- Hide quoted text -

- Show quoted text -

so sorry.. i was using modelsim to run the code with
'ELSIF(rising_edge(CLK) or falling_edge(CLK))THEN'.. it works when i
was using modelsim, but when i try to implement the design, it shows
an error "unsupported Clock statement".

may i know if there is anyways to implement? thanks a million

 

[Tricky]

so sorry.. i was using modelsim to run the code with
'ELSIF(rising_edge(CLK) or falling_edge(CLK))THEN'.. it works when i
was using modelsim, but when i try to implement the design, it shows
an error "unsupported Clock statement".

may i know if there is anyways to implement? thanks a million

Probably because the registers in the Target device you are using only
support rising clock edges.

Use a PLL to multiply your clock by 2, and then clock this process
with the 2x clock, always activated on rising edges of the new clock.

 

[Andy]

Probably because the registers in the Target device you are using only
support rising clock edges.

Use a PLL to multiply your clock by 2, and then clock this process
with the 2x clock, always activated on rising edges of the new clock.

Besides doubling the clock, or using double data rate IO registers,
there is a trick using two flops and three XOR gates to implement DDR
register functionality with only single edge flops (yielding a glitch
free output without clock gating/muxing). A search of this newsgroup
will return lots of info on it. For all but the smallest uses, it is
more efficient to double the clock if you have those resources.

Andy

 

[Ralf Hildebrandt]

i have 3 processes in my code, all running with a shared counter.

You asked this some time ago and got a hint. You did not respond to the
hint.

counter counts from 0 to 99.
process1(rising edge)
take in a sample at the rising edge, so in total i will have 100
samples.

process2(falling edge)
take in a sample at the falling edge, so in total i will have another
100 samples.

Up to here - no problem.

process3(rising edge)
add up the samples for the previous 2 processes.

No. I gave you the hint, that the 3rd process is pure combinational
process. (Indeed - it is no logic at all.) You simple need to assign the
1st sample of the rising_edge sample vector to the 1st position of the
complete sample vector, the 1st sample of the falling_edge sample vector
to the 2nd position of the complete sample vector, the 2nd sample of the
rising_edge sample vector to the 3rd position of the complete sample
vector and so on...

sample_vector_complete sample_vector_rising sample_vector_falling
1 1 -
2 - 1
3 2 -
4 - 2
5 3 -
.... and so on.

Use a for-loop.


Ralf

 

[raullim7]

You asked this some time ago and got a hint. You did not respond to the
hint.



Up to here - no problem.


No. I gave you the hint, that the 3rd process is pure combinational
process. (Indeed - it is no logic at all.) You simple need to assign the
1st sample of the rising_edge sample vector to the 1st position of the
complete sample vector, the 1st sample of the falling_edge sample vector
to the 2nd position of the complete sample vector, the 2nd sample of the
rising_edge sample vector to the 3rd position of the complete sample
vector and so on...

sample_vector_complete sample_vector_rising sample_vector_falling
1 1 -
2 - 1
3 2 -
4 - 2
5 3 -
... and so on.

Use a for-loop.

Ralf

hi, i tried this method but got an error.
sample : IN STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
sample_rising : IN STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
sample_falling : IN STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
sample_complete : OUT STD_LOGIC_VECTOR(8 DOWNTO 0):= (OTHERS => '0');

IF(COUNTER > 0) THEN
count := COUNTER;
Vout_temp1(count) <= Vout;
END IF;

error "Type of Vout_temp1 is incompatible with type of Vout."

may i know how can i resolve this problem?

 

[Ralf Hildebrandt]

hi, i tried this method but got an error.
sample : IN STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
sample_rising : IN STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
sample_falling : IN STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
sample_complete : OUT STD_LOGIC_VECTOR(8 DOWNTO 0):= (OTHERS => '0');

Don't use default values for input or output ports.

Wouldn't it be a good idea, if the length of sample_complete is twice
the length of sample_rising / sample_falling?

IF(COUNTER > 0) THEN
count := COUNTER;
Vout_temp1(count) <= Vout;
END IF;

error "Type of Vout_temp1 is incompatible with type of Vout."

I can't see the related definition of vout_temp1 and Vout. Obviously
Vout_temp1 is some kind of array and Vout should be of the same type as
one element of the array Vout_temp1

may i know how can i resolve this problem?

Check the definition of Vout_temp1 and Vout. As the error message says:
they are not compatible.


Ralf